To realize high-speed computations in a residue number system (RNS), an implementation method for residue arithmetic circuits using signed-digit (SD) number representation is proposed. Integers mp = (2p-1) known as Mersenne numbers are used as moduli, so that modulo mp addition can be performed by an end-around-carry SD adder and the addition time is independent of the word length of operands. Using a binary modulo mp SD adder tree, the modulo mp multiplication can be performed in a time proportional to log2p.

A wideband beamformer with mainlobe control is proposed. To make the beamformer robust against pointing errors, inequality rather than equality constraints are used to restrict the mainlobe response, thus more degrees of freedom are saved. The constraints involved are nonconvex, therefore are linearly approximated so that the beamformer can be obtained by iterating a second-order cone program. Moreover, the response variance element is introduced to achieve a frequency invariant beamwidth. The effectiveness of the technique is demonstrated by numerical examples.

To improve speech coding quality, in particular, the long-term dependency prediction characteristics, we propose a new nonlinear predictor, i. e. , a fully connected recurrent neural network (FCRNN) where the hidden units have feedbacks not only from themselves but also from the output unit. The comparison of the capabilities of the FCRNN with conventional predictors shows that the former has less prediction error than the latter. We apply this FCRNN instead of the previously proposed recurrent neural networks in the code-excited predictive speech coding system (i. e. , CELP) and shows that our system (FCRNN) requires less bit rate/frame and improves the performance for speech coding.

The performance of spectrum sensing in cognitive radio can be improved by employing multiple antennas. In this letter, the effect of antenna correlation on the performance improvement by deploying multiple antennas in the sensing node of the secondary system is investigated. It is proved mathematically that in the regime of low SNR, with antenna correlation, the secondary sensing node can achieve almost the same performance improvement as that without correlation. Simulation results verify the conclusions.

A new near-field source localization algorithm based on a uniform linear array was proposed. The proposed algorithm estimates each parameter separately but does not need pairing parameters. It can be divided into two important steps. The first step is bearing-related electric angle estimation based on the ESPRIT algorithm by constructing a special cumulant matrix. The second step is the other electric angle estimation based on the 1-D MUSIC spectrum. It offers much lower computational complexity than the traditional near-field 2-D MUSIC algorithm and has better performance than the high-order ESPRIT algorithm. Simulation results demonstrate that the performance of the proposed algorithm is close to the Cramer-Rao Bound (CRB).

Major challenges of the conventional spread-transform dither modulation (STDM) watermarking approach are two-fold: (i) it exploits a fixed watermarking strength (more particularly, the quantization index step size) to the whole cover image; and (ii) it is fairly vulnerable to the amplitude changes. To tackle the above challenges, an adaptive spread-transform dither modulation (ASTDM) approach is proposed in this paper for conducting robust color image watermarking by incorporating a new perceptual model into the conventional STDM framework. The proposed approach exploits a new perceptual model to adjust the quantization index step sizes according to the local perceptual characteristics of a cover image. Furthermore, in contrast to the conventional Watson's model is vulnerable to the amplitude changes, our proposed new perceptual model makes the luminance masking thresholds be consistent with any amplitude change, while keeping the consistence to the properties of the human visual system. In addition, certain color artifacts could be incurred during the watermark embedding procedure, since some intensity values are perceptibly changed to label the watermark. For that, a color artifact suppression algorithm is proposed by mathematically deriving an upper bound for the intensity values according to the inherent relationship between the saturation and the intensity components. Extensive experiments are conducted using 500 images selected from Corel database to demonstrate the superior performance of the proposed ASTDM approach.

In non-destructive testing (NDT), ultrasonic echo is often an overlapping multi-echo signals with noise. However, the accurate estimation of ultrasonic time-of-flight (TOF) is essential in NDT. In this letter, a novel method for TOF estimation through envelope is proposed. Firstly, the wavelet denoising technique is applied to the noisy echo to improve the estimation accuracy. Then, the Hilbert transform (HT) is used in ultrasonic signal processing in order to extract the envelope of the echo. Finally, the TOF of each component of multi-echo signals is estimated by the local maximum point of signal envelope. Furthermore, the time resolution of time-overlapping ultrasonic echoes is discussed. Numerical simulation has been carried out to show the performances of the proposed method in estimating TOF of ultrasonic signal.

The separation time-overlapping ultrasound signals is necessary to obtain accurate estimate of transit time and material properties. In this letter, a method to determine the optimal transform order of fractional Fourier transform (FRFT) for decomposition of overlapping ultrasonic signals is proposed. The optimal transform order is obtained by minimizing the mean square error (MSE) between the output and the reference signal. Furthermore, windowing in FRFT domain is discussed. Numerical simulation results show the performances of the proposed method in separating signals overlapping in time.

An audio signal level compressor is presented, which is based on the approximation algorithm using an interpolating polynomial. To implement a compression characteristic in a digital audio system, a power calculation with fractional numbers is required and it is difficult to be performed directly in digital circuits. We introduce a polynomial expression to approximate the power operation, then the gain calculation is easily performed with a number of additions, multiplications and a division. Newton's interpolation formula is used to calculate the compression characteristics in a very short time and the obtained compression characteristics are very close to the ideal ones.

In this letter, we propose a Cooperation-aware topology control scheme with Opportunistic Interference Cancellation (COIC) to improve network capacity in wireless ad hoc networks by jointly considering both upper layer network capacity and physical layer cooperative communications with interference cancellation. We show that the benefits brought by cooperative communications are opportunistic and rely on network structures and channel conditions. Such opportunistic advantages have significant impacts on network capacity, and our proposed COIC can effectively capture these opportunities to substantially improve network capacity.

A compact residue arithmetic multiplier based on the radix-4 signed-digit arithmetic is presented. Conventional residue arithmetic circuits have been designed using binary number arithmetic system, but the carry propagation arises which limits the speed of arithmetic operations in residue modules. In this paper, two radix-4 signed-digit (SD) number representations, {-2,-1,0,1,2} and {-3,-2,-1,0,1,2,3}, are introduced. The former is used for the input and output, and the later for the inner arithmetic circuit of the presented multiplier. Integers 4p and 4p 1 are used as moduli of residue number system (RNS), where p is a positive integer and both circuits for partial product generation and sum of the partial products can be efficiently constructed by using the multiple-valued current-mode circuits. The modulo m addition, m=4p or m=4p 1, can be performed by an SD adder or an end-around-carry SD adder with the multiple-valued circuits and the addition time is independent of the word length of operands. The modulo m multiplier can be compactly constructed using a binary tree of the multiple-valued modulo m SD adders, and consequently the modulo m multiplication is performed in O(log p) time. The number of MOS transistors required in the presented residue arithmetic multiplier is about 86p2 + 66p.

Based on the least square (LS) approximation of sinusoidal signal in frequency domain by sample data, a frequency estimator is derived. Since sinusoidal signals are narrow-banded whereas white noise spreads equally in the whole spectrum, only narrow-band approximation around the actual tone is needed, and thus the influence of noise can be decreased significantly with high computational efficiency. Experimental results show that, without any iterations, the performance of the proposed estimator is close to the Cramer-Rao Bound (CRB), and has a lower SNR threshold compared with other existing estimators.

Role-based access control (RBAC) model has been widely recognized as an efficient access control model and becomes a hot research topic of information security at present. However, in the large-scale enterprise application environments, the traditional RBAC model based on the role hierarchy has the following deficiencies: Firstly, it is unable to reflect the role relationships in complicated cases effectively, which does not accord with practical applications. Secondly, the senior role unconditionally inherits all permissions of the junior role, thus if a user is under the supervisor role, he may accumulate all permissions, and this easily causes the abuse of permission and violates the least privilege principle, which is one of the main security principles. To deal with these problems, we, after analyzing permission types and role relationships, proposed the concept of atom role and built an atom-role-based access control model, called ATRBAC, by dividing the permission set of each regular role based on inheritance path relationships. Through the application-specific analysis, this model can well meet the access control requirements.

A new frequency estimator for a single real-valued sinusoid signal in white noise is proposed. The new estimator uses the Pisarenko Harmonic Decomposer (PHD) estimator to get a coarse frequency estimate and then makes use of multiple correlation lags to obtain an adjustment term. For the limited-length single sinusoid, its correlation has the same frequency as itself but with a non-zero phase. We propose to use Taylor series to expand the correlation at the PHD coarse estimated frequency with amplitude and phase of the correlation into consideration. Simulation results show that this new method improves the estimation performance of the PHD estimator. Moreover, when compared with other existing estimator, the mean square frequency error of the proposed method is closer to the Cramer-Rao Lower Bound (CRLB) for certain SNR range.

A method for the synthesis of near optimal NAND networks is presented. At first, a given logical function is realized as a multilevel network with a minimum number of negative gates. Next this is transformed into a NAND network. Since procedures presented here do not require backtracking, they are quite efficient.

A novel residue arithmetic algorithm using radix-2 signed-digit (SD) number representation is presented. By this representation, memoryless residue arithmetic circuits using SD adders can be implemented. Conventional residue arithmetic circuits have been designed using binary number arithmetic system, but the carry propagation arises which limits the speed of arithmetic operations in residue modules. In this paper, a p-digit radix-2 SD number system is introduced to simplify the residue operation. For a modulus m, 2p-1 m 2p+2p-1-1, in a residue number system (RNS), the modulo m addition is performed by using two p-digit SD adders, one for the addition and one for the residue operation. Thus, the modulo m addition time is independent of the word length of operands. When m=2p or m= 2p 1, the modulo m addition is implemented by using only one SD adder. Moreover, a modulo m multiplier is constructed using a binary modulo m SD adder tree, and the modulo m multiplication can be performed in a time proportional to log 2 p. The VHDL implementation method for the presented algorithm is also discussed. The design and simulation results of some residue arithmetic circuits show that high speed residue arithmetic circuits can be obtained by the presented algorithms.

Low-complexity joint subcarrier and power allocation is considered. The applied criterion is to minimize the transmission power while satisfying the users' rate requirements. Subcarrier and power allocation are separately applied. Fixed spectrum efficiency is assumed to simplify the subcarrier allocation. We show that under fixed spectrum efficiency, power allocation can be obtained by solving some sets of linear equations. Simulation result shows the effectiveness of the proposed algorithm.