A small-sized leakage-controlled gated sense amplifier (SA) and relevant circuits are proposed for 0.5-V multi-gigabit DRAM arrays. The proposed SA consists of a high-VT PMOS amplifier and a low-VT NMOS amplifier which is composed of high-VT NMOSs and a low-VT cross-coupled NMOS, and achieves 46% area reduction compared to a conventional SA with a low-VT CMOS preamplifier. Separation of the proposed SA and a data-line pair achieves a sensing time of 6 ns and a writing time of 0.6 ns. Momentarily overdriving the PMOS amplifier achieves a restoring time of 13 ns. The gate level control of the high-VT NMOSs and the gate level compensation circuit for PVT variations reduce the leakage current of the proposed SA to 2% of that without the control, and its effectiveness was confirmed using a 50-nm test chip.

A gated sense amplifier (GSA) consisting of a low-Vt gated preamplifier (LGA) and a high-Vt sense amplifier (SA) is proposed. The gating scheme of the LGA enables quick amplification of an initial cell signal voltage (vS0) because of its low Vt and prevents the cell signal from degrading due to interference noise between data lines. As for a conventional sense amplifier (CSA), this new type of noise causes sensing error, and the noise-generation mechanism was clarified for the first time by analysis of vS0. The high-Vt SA holds the amplified signal and keeps subthreshold current low. Moreover, the gating scheme of the low-Vt MOSFETs in the LGA drives the I/O line quickly. The GSA thus simultaneously achieves fast sensing, low-leakage data holding, and fast I/O driving, even for sub-1-V mid-point sensing. The GSA is promising for future sub-1-V gigabit dynamic random-access memory (DRAM) because of reduced variations in the threshold voltage of MOSFETs; thus, the offset voltage of the LGA is reduced. The effectiveness of the GSA was verified with a 70-nm 512-Mbit DRAM chip. It demonstrated row access time (tRCD) of 16.4 ns and read access (tAA) of 14.3 ns at array voltage of 0.9 V.

A small data-line-swing read/write scheme is described for half-Vcc plate nonvolatile DRAMs with ferroelectric capacitors designed to achieve high reliability for read/write operations. In this scheme, the normal read/write operation holds the data as a charge with a small data-line-swing, and the store operation provides sufficient polarization with a full data-line-swing. This scheme enables high read/write endurance, because the small data-line-swing reduces the fatigue of the ferroelectric capacitor. Two circuit technologies are used in this scheme to increase the operating margin. The first is a plate voltage control technique that solves the polarization retention problem of half-Vcc plate nonvolatile DRAM technologies. The second is a doubled data-line-capacitance recall technique that connects two data lines to a cell and enlarges the readout signal compared to normal operation, when only one data line is connected to a cell. These techniques and circuits improve the write-cycle endurance by almost three orders of magnitude, while reducing the array power consumption during read/write operations to one-third that of conventional nonvolatile DRAMs.

The crystallization process of Sr0. 7Bi2. 3Ta2O9 (SBT) ferroelectric thin films with different crystal orientations formed by chemical liquid deposition using an alkoxide precursor was investigated. One film showed strong c-axis orientation (a-type film), while another shows scarcely any c-axis orientation (b-type film). We report that the crystallization process was the same even when crystal orientation differed. Thin films first change from amorphous to fluorite fine grains; the fluorite grains then change to bismuth layer-structure grains. The different orientation of the SBT films is not caused by different crystallization process. Both SBT films with different crystal orientations consist of fine fluorite grains after 650 heat-treatment. Their leakage current density characteristics differ, however. The leakage current density of the a-type film was independent of the electric field, and showed a low value of 10-8 A/cm2. The leakage current density of the b-type film, however, was dependent on the electric field, and increased continuously with the increasing electric field. After 700 heat-treatment, both films consist of large grains with bismuth layer-structure and fine fluorite grains. The matrix of both films contains large grains with bismuth layer-structure that determines the leakage current density characteristics. Since the fluorite grain size after a 700 heat-treatment is the same as that after 650 heat-treatment, nucleation is predominant at the structural phase boundary from amorphous to fluorite. The bismuth layer-structure grains are large and single-crystal grains after both a 700 and 800 heat-treatment. Increased grain size predominates at the structural phase boundary from fluorite to bismuth layer-structure grains. Clearly, ferroelectric SBT films with bismuth layer-structure are crystallized in two steps, each having a different predominant crystal growth mechanism.

The potential distribution around a linear array of donor atoms in a semiconductor crystal is calculated, approximating the linear array by a continuous line charge. Two methods are used for the analysis. One is the self-consistent calculation of Poisson's equation and the effective mass Schrödinger's equation, and the other is the Thomas-Fermi approximation. Results of both methods agree very well, and it is shown that it is possible to form a potential distribution as fine as the electron wavelength by appropriate arrangement of the impurity atoms. Arrays of impurity atoms therefore can act as buiding elements for future electron wave devices.

With the aim of applying a MISS tunnel-diode cell to a high-density RAM, we studied its problems and developed three circuit technologies to solve them. The first, a standby-voltage control scheme, reduces standby currents and increases the signal current by 3.4 times compared to the conventional one. The second, a hierarchical bit-line structure, reduces the number of memory cells in a bit-line without increasing the number of sense amplifiers. The third, a twin-dummy-cell technique, generates a proper reference signal to discriminate read currents. These technologies enable a capacitorless MISS diode cell with an effective cell area of 6F 2 (F: minimum feature size) to be applied to a high-density RAM.

A DRAM-cell array with 12-F2 twin cell was developed and evaluated in terms of speed, retention time, and low-voltage operation. The write and read-out times of the twin-cell array are shorter than those of a single-cell array by 70% and 40% respectively, because of parallel writing and reading of half charge to and from two memory cells. According to measured retention characteristics of the single cells, the twin-cell array improves retention time by 20% compared with the single-cell array at 1 V and keeps the retention time of the single-cell array at 0.4 V. Furthermore, the cell accepts the plate-driven scheme without the need of a dummy cell, lowering the necessary word-line voltage by 0.4 V.