This paper describes 3-GHz and 7-GHz tunable-inductance LC-tank voltage-controlled oscillators (VCOs) implemented in 0.18-µm CMOS technology. Unlike the traditional tuning method by a varactor, a tunable inductor is employed in the VCO by using a transformer to compensate for the energy loss. The VCO facilitates the tuning frequency and low noise of the output signals, together with a variable inductor which satisfies both criteria. The 3-GHz VCO using a symmetry transformer provides the tuning range of 2.85 to 3.12 GHz at 1-V supply. The power consumption is 4.8 mW while the measured phase noise is -126 dBc/Hz at 1-MHz offset from a 2.85-GHz carrier. A small-area stacked transformer is employed in the 7-GHz VCO, which achieves a tuning range of 6.59 to 7.02 GHz and measured phase noise of -114 dBc/Hz at 1-MHz offset from a 6.59-GHz carrier while consuming 9 mW from a 1.2-V supply.

Testing is a critical stage in integrated circuits production in order to guarantee reliability. The complexity and high integration level of mixed-signal ICs has put forward new challenges to circuit testing. This paper describes an oscillation-based combined self-test strategy for the analog portion and analog-to-digital converters (ADCs) in integrated mixed-signal circuits. In test mode, the analog portion under test is reconfigured into an oscillator, generating periodic signals as the test stimulus of ADC. By analyzing the A/D conversion results, a histogram test of ADC can be performed, and the oscillation frequency as well as amplitude can be checked, and in this way the oscillation test of the analog portion is realized simultaneously. For an analog benchmark circuit combined with an ADC, triangle oscillation and sinusoid oscillation schemes are both given to test their faults. Experimental results show that fault coverage of the analog portion is 92.2% and 94.3% in the two schemes respectively, and faults in the ADC can also be tested.

Process variation causes significant fluctuations in the timing performance of analog circuits, which causes a fraction of circuits to fail specifications. By testing the delay-performance, we can recognize the failed circuits during production testing. In this paper, we have proposed a low overhead and process tolerant delay evaluation circuit for built-in self test (BIST) function for analog differential circuits. This circuit contains a delay generation cell, an input differential signal generation cell, a delay matching cell, a sample-hold circuit, and a comparator. This circuit was implemented with 0.18 µm CMOS process. Simulation results over process variation, devices mismatch and layout parasitics, but without silicon measurement, show that the accuracy in delay detection is within 5 ps. A case study was done over a feed-forward equalizer (FFE). A typical use of this circuit is testing the delay of various FIR (Finite Impulse Response) filters.

Currently, visual perceptions generated by visual prosthesis are low resolution with unruly color and restricted grayscale. This severely restricts the ability of prosthetic implant to complete visual tasks in daily scenes. Some studies explore existing image processing techniques to improve the percepts of objects in prosthetic vision. However, most of them extract the moving objects and optimize the visual percepts in general dynamic scenes. The application of visual prosthesis in daily life scenes with high dynamic is greatly limited. Hence, in this study, a novel unsupervised moving object segmentation model is proposed to automatically extract the moving objects in high dynamic scene. In this model, foreground cues with spatiotemporal edge features and background cues with boundary-prior are exploited, the moving object proximity map are generated in dynamic scene according to the manifold ranking function. Moreover, the foreground and background cues are ranked simultaneously, and the moving objects are extracted by the two ranking maps integration. The evaluation experiment indicates that the proposed method can uniformly highlight the moving object and keep good boundaries in high dynamic scene with other methods. Based on this model, two optimization strategies are proposed to improve the perception of moving objects under simulated prosthetic vision. Experimental results demonstrate that the introduction of optimization strategies based on the moving object segmentation model can efficiently segment and enhance moving objects in high dynamic scene, and significantly improve the recognition performance of moving objects for the blind.

An injection-locked clock recovery circuit (CRC) with quadrature outputs based on multiplexed oscillator is presented. The CRC can operate at a half-rate speed to provide an adequate locking range with reasonable jitter and power consumption because both clock edges sample the data waveforms. Implemented by 0.18-µm CMOS technique, experimental results demonstrate that it can achieve the phase noise of the recovered clock about -121.55 dBc/Hz at 100-kHz offset and -129.58 dBc/Hz at 1-MMz offset with 25 MHz lock range, while operating at the input data rate of 1.55 Gb/s.

Introduction of Fully Convolutional Networks (FCNs) has made record progress in salient object detection models. However, in order to retain the input resolutions, deconvolutional networks with unpooling are applied on top of FCNs. This will cause the increase of the computation and network model size in segmentation task. In addition, most deep learning based methods always discard effective saliency prior knowledge completely, which are shown effective. Therefore, an efficient salient object detection method based on deep learning is proposed in our work. In this model, dilated convolutions are exploited in the networks to produce the output with high resolution without pooling and adding deconvolutional networks. In this way, the parameters and depth of the network are decreased sharply compared with the traditional FCNs. Furthermore, manifold ranking model is explored for the saliency refinement to keep the spatial consistency and contour preserving. Experimental results verify that performance of our method is superior with other state-of-art methods. Meanwhile, the proposed model occupies the less model size and fastest processing speed, which is more suitable for the wearable processing systems.

Novel dual-band bandpass filter (BPF) with quasi-elliptic function response by using the meander coupled step-impedance resonators (SIRs) is presented. By tuning the appropriate impedance ratio (K) and physical length of SIRs, the BPF has good dual-band performance at 2.4 and 5.2 GHz with high selectivity, due to the transmission zeros appeared in two passband edges. Measured results of the proposed BPF have a good agreement with the electromagnetic (EM) simulated results.

Restoration is an important area in improving the visual quality, and lays the foundation for accurate object detection or terrain classification in image analysis. In this paper, we introduce Beta process priors into hierarchical sparse Bayesian learning for recovering underlying degraded hyperspectral images (HSI), including suppressing the various noises and inferring the missing data. The proposed method decomposes the HSI into the weighted summation of the dictionary elements, Gaussian noise term and sparse noise term. With these, the latent information and the noise characteristics of HSI can be well learned and represented. Solved by Gibbs sampler, the underlying dictionary and the noise can be efficiently predicted with no tuning of any parameters. The performance of the proposed method is compared with state-of-the-art ones and validated on two hyperspectral datasets, which are contaminated with the Gaussian noises, impulse noises, stripes and dead pixel lines, or with a large number of data missing uniformly at random. The visual and quantitative results demonstrate the superiority of the proposed method.

In Long-Term Evolution (LTE)-Advanced, an important goal in addition to achieving high-speed, high-capacity communications is throughput enhancement for cell-edge users. One solution is to relay radio transmissions between an eNode B and user equipment (UE). Relays are expected to extend the coverage to the cell boundary and coverage hole areas, and are expected to reduce network costs. It was agreed that in Release 10 LTE, a Layer-3 (L3) relay, which achieves self-backhauling of radio signals between an eNode B and a UE in Layer 3 should be standardized. Meanwhile, a Layer-1 (L1) relay, which amplifies and forwards received radio frequency signals, has already found widespread use in second-generation and third-generation mobile communication systems. This paper investigates the downlink system level performance for L3 and L1 relays with orthogonal frequency division multiple access (OFDMA) in LTE-Advanced. Various practical factors are taken into account in the evaluations such as the processing delay and upper bound of the amplifier gain of the L1 relay, capacity limitation of the backhaul channels, and empty buffer status at the L3 relay. We also propose and investigate a downlink backhaul link (radio link between the eNode B and L3 relay node) scheduling method for the in-band half-duplex L3 relay. In the proposed scheduling method, radio resources from an eNode B to an L3 relay node and macro UE are multiplexed in the same backhaul subframe considering the number of relay UEs and macro UEs, and the channel quality of the backhaul link to the L3 relay and the access link to the macro UE. Based on system-level simulations, we clarify the system impact of several conditions for the relay such as the number of relay nodes and the number of backhaul (radio link between eNode B and L3 relay) subframes, the distance between the eNode B and relay, and show the throughput performance gain of the L3 relay compared to the L1 relay. We also clarify that the cell-edge UE throughput performance is increased by approximately 10% by applying the proposed scheduling method due to more efficient and fair resource allocation to the L3 relay and macro UEs.

This paper proposes a parallel coupled microstrip bandpass filter (BPF) with ring Electromagnetic Bandgap (EBG) cells on the middle layer for spurious suppression. The ring EBG cells of the middle layer add a good stopband-rejection mode to the second harmonics of the parallel coupled microstrip BPF with suppression of over -50 dB, without affecting the center frequency and insertion loss of the original designed BPF. The design of ring EBG cells is presented and verified by the experimented results.

This investigation proposes a novel dual-mode patch bandpass filter (BPF) that uses defect ground structure (DGS) to suppress spurious response. The proposed dual-mode patch BPF has exhibits a wide stopband characteristic owing to that uses the bandgap resonant characteristic of DGS in the harmonic frequency of the dual-mode patch BPF. The novel proposed filter demonstrates the frequency characteristics with center frequency f0 = 2.2 GHz, 3-dB bandwidth (FBW) of 8% and wider stopband from 2.6 to 6 GHz at the level of -35 dB. The experimental and simulated results agree.

In this paper, a compact ultra-wideband bandpass filter (UWB-BPF) using pseudo-interdigital stepped-impedance resonators (PIDT-SIRs) is designed and implemented on a commercial printed circuit board (PCB) of RT/Duroid 5880 substrate. The first two resonant modes of the SIR are coupled together and they are applied to create a wide passband. The proposed filter at center frequency f0 of 7.1 GHz has very good measured characteristics including the bandwidth of 3.68-10.46 GHz (3-dB fractional bandwidth of 95%), low insertion loss of -0.50.4 dB, sharp rejection due to two transmission zeros in the passband edge created by the inter-stage coupling. Experimental results of the fabricated filter show a good agreement with the predicted results.

This paper proposes a novel dual-mode ring bandpass filter (BPF) using defect ground structure (DGS). The proposed filter provides wide stopband characteristic resulted from the bandgap characteristic of DGS for suppressing spurious response of the dual-mode ring BPF. The H shaped DGS cell is modeled as a parallel LC resonator and the equivalent circuit parameters are extracted. The relationship between bandgap characteristic and design parameters of DGS dimension is discussed and the bandgap characteristic of DGS on the filter performance is also investigated. The novel proposed filter has the frequency characteristics with a central frequency f0 = 7.7 GHz, a 3-dB bandwidth of 4.5% and wider stopband from 9 to 15.5 GHz at the level of -35 GHz. Measured results of experimental filter has good agreement with the theoretical simulation results.

A clock and data recovery (CDR) circuit using a new half-rate wide-range phase detection technique has been developed. Unlike the conventional three-state phase detectors, the proposed detector is applicable to the Non-Return-to-Zero (NRZ) data stream and also has low jitter and wide capture range characteristics. The CDR circuit was implemented in a 0.35-µm N-well CMOS technique. Experimental results demonstrate that it can achieve the peak-to-peak jitter of the recovered clock and the retimed data about 120 ps and 170 ps, respectively, while operating at the input data rate of 1 Gb/s. The total power dissipation of the CDR is 64.8 mW for the supply 3 V.

This investigation proposes a modified equivalent circuit of single complementary split-ring resonator (CSRR) in planar transmission media and a dual-mode ring bandpass filter (BPF) that uses periodic CSRRs to suppress the spurious response. The proposed modified equivalent circuit consists of lumped elements that can be easily extracted from the measured S parameters. The proposed dual-mode ring BPF has exhibits a wide stopband characteristic owing to the bandgap resonant characteristic of CSRRs in the harmonic frequency of the dual-mode ring BPF. Good agreement with EM simulation and measurement is demonstrated.

Carrier aggregation (CA) is one of the most important techniques for LTE-Advanced because of its capability to support a wide transmission bandwidth of up to 100 MHz and heterogeneous networks effectively while achieving backward compatibility with the Release 8 LTE. In order to improve the performance of control information transmission in heterogeneous networks, cross-carrier scheduling is supported, i.e., control information on one component carrier (CC) can assign radio resources on another CC. To convey the control information efficiently, a search space is defined and used in Release 8 LTE. In cross-carrier scheduling, the optimum design for the search space for different CCs is a paramount issue. This paper presents two novel methods for search space design. In the first method using one hash function, a user equipment (UE)-specific offset is introduced among search spaces associated with different CCs. Due to the UE-specific offsets, search spaces of different UEs are staggered and the probability that the search space of one UE is totally overlapped by that of another UE can be greatly reduced. In the second method using multiple hash functions, a novel randomization scheme is proposed to generate independent hash functions for search spaces of different CCs. Because of the perfect randomization effect of the proposed method, search space overlapping of different UEs is reduced. Simulation results show that both the proposed methods effectively reduce the blocking probability of the control information compared to existing methods.

A high-speed triangular-modulated spread-spectrum clock generator using a fractional phase-locked loop is presented. The fractional division is implemented by a nested fractional topology, which is constructed from a dual-modulus divide-by-(N-1/16)/N divider to divide the VCO outputs as a first division period and a fractional control circuit to establish a second division period to cause the overall fractional division. The dual-modulus divider introduces a delay-locked-loop network to achieve phase compensation. Operating at the frequency of 3.2 GHz, the measured peak power reduction is around 16 dB for a deviation of 0.37% and a frequency modulation of 33 kHz. The circuit occupies 1.41.4 mm2 in a 0.18-µm CMOS process and consumes 52 mW.

In this paper, we further study linear network error correction code on a multicast network and attempt to establish a connection between linear network error correction codes and representable matroids. We propose a similar but more accurate definition of matroidal error correction network which has been introduced by K. Prasad et al. Moreover, we extend this concept to a more general situation when the given linear network error correction codes have different error correcting capacity at different sinks. More importantly, using a different method, we show that a multicast error correction network is scalar-linearly solvable if and only if it is a matroidal error correction network.

In this letter, a 1.25-Gb/s 0.18-µm CMOS half-rate burst-mode clock and data recovery (CDR) circuit is presented. The CDR contains a fast-locking clock recovery circuit (CRC) using a realigned oscillation technique to recover the desired clock. To reduce the power dissipation, the CRC uses a two-stage ring structure and a current-reused concept to merge with an edge detector. The recovered clock has a peak-to-peak jitter of 34.0 ps at 625 MHz and the retimed data has a peak-to-peak jitter of 44.0 ps at 625 Mb/s. The occupied die area of the CDR is 1.41.4 mm2, and power consumption is 32 mW under a 1.8-V supply voltage.

We show a tracking attack against the newest ID-transfer scheme for low-cost RFID tags. In this attack, a wide attacker, i.e. an attacker that can access the verification result of a server, is able to forge a set of specific messages, and to track a tag. The attack is unique as it involves three sessions of the protocol. Finally, a simple feasibility analysis of the attack is given.