This paper presents a novel and successful optimization algorithm for optimizing Multiple-valued Logic (MVL) functions based on Petri net theory. Mathematical properties and Petri net modeling tools to implement MVL systems are introduced. On the basis of these properties and modeling tools, the optimization algorithm can synthesize, analyze and minimize an arbitrary quaternary logic function of n-input variables. The analysis technique of optimization algorithm is a well-established concept from both theories of MVL and Petri nets, and this can be applied to specify and optimize any MVL Petri net system. In this paper, Petri nets of Galois field have been proposed in order to form a complete system, which can be used to realize and construct VLSI circuit of any MVL function. Based on the Petri nets of Galois field and the proposed algorithm, the quaternary minimum and maximum functions have been analyzed, minimized, and designed. These applications have demonstrated the usefulness of optimization algorithm. Based on Petri net theory, the analysis revealed important information about MVL Petri net modeled systems, where this information has been used to evaluate the modeled system and suggest improvements or changes. For evaluation, advantages of the proposed method over a conventional logic minimization method are presented. Also, we have observed that the MVL Petri nets have the following advantages: Designers can exhibit clearly, simply and systematically any complex MVL Petri net nodel, number of concurrent operations is increased, number of places and transitions that are needed to realize a MVL model is very small, and the interconnection problems can be greatly reduced.

A globally and quadratically convergent algorithm is presented for solving nonlinear resistive networks containing transistors modeled by the Gummel-Poon model or the Shichman-Hodges model. This algorithm is based on the Katzenelson algorithm that is globally convergent for a broad class of piecewise-linear resistive networks. An effective restart technique is introduced, by which the algorithm converges to the solutions of the nonlinear resistive networks quadratically. The quadratic convergence is proved and also verified by numerical examples.

This paper considers algebraic basic processes, a subset of communicating processes in CCS by Milner, and presents a synthesis algorithm to infer a process that satisfies the properties of the process, represented as fomulae in Hennessy-Milner Logic. The validity of the proposed algorithm can be stated that it synthesizes a process in the limit, which cannot be distinguished from the target one with respect to the strong equivalence.

Nonmonotonic reasoning is a logical inference system which attempts to approximate human commonsense reasoning and is characterized as defeasible: having reasonably drawn a conclusion from some premises we may be forced to retract that conclusion upon learning new facts. This paper introduces a Petri net model for nonmonotonic reasoning with nonmonotonic rules generated by annotated logic programs and the unless operator. In the Petri net model, a fixpoint of a nonmonotonic theory can be represented as a maximal and consistent support of a firing sequence. We propose a structural method for finding extensions (coherent consequences) for a given set of nonmonotonic logic rules. It is based on the T-invariant technique for testing fireability of a goal transition in the Petri net model of Horn clause logic programs.

We developed a simple, practical, adaptive data compression algorithm of the LZ78 class. According to the Lempel-Ziv greedy parsing, a string boundary is not related to the statistical history modeled by finite-state sources. We have already reported an algorithm classifying data into subdictionaries (CSD), which uses multiple subdictionaries and conditions the current string by using the previous one to obtain a higher compression ratio. In this paper, we present a practical implementation of this method suitable for any kinds of data, and show that CSD is more efficient than the LZC which is the method used by the program compress available on UNIX systems. The CSD compression performance was about 10% better than that of LZC with the practical dictionary size, an 8k-entry dictionary when the test data was from the Calgary Compression Corpus. With hashing, the CSD processing speed became as fast as that of LZC, although the CSD algorithm was more complicated than LZC.

A new steepest descent linear adaptive algorithm, called the proportion-sign algorithm (PSA), is introduced and its performance analysis is presented when the signals are from zero-mean jointly stationary Gaussian processes. The PSA improves the convergence speed over the least mean square (LMS) algorithm without overly degrading the steady-state error performance and has the robustness to impulsive interference occurring in the desired response by adding a minimal amount of computational complexity. Computer simulations are presented that show these advantages of the PSA over the LMS algorithm and demonstrate a close match between theoretical and empirical results to verify our analysis.

A design of a high power laser structure is presented which is based on an increase of the cavity length as well as a maximization of the stripe width. This requires a low value for the modal attenuation coefficent and a low optical confinement factor. A model is presented from which the modal gain, the confinement factor, the active region thickness, the stripe width, the length and the reflection coefficients can be calculated. A variant for all design parameters needed to reach 1 W emission in the fundamental lateral mode is given. These values are used to design the epitaxial structure.

The classical supervised learning algorithms for optimizing multi-layered feedforward neural networks, such at the original back-propagation algorithm, suffer from several weaknesses. First, they have the possibility of being trapped at local minima during learning, which may lead to failure in finding the global optimal solution. Second, the convergence rate is typically too slow even if the learning can be achieved. This paper introduces a new learning algorithm which employs a genetic-type search during the learning phase of back-propagation algorithm so that the above problems can be overcome. The basic idea is to evolve the network weights in a controlled manner so as to jump to the regions of smaller mean squared error whenever the back-propagation stops at a local minimum. By this, the local minima can always be escaped and a much faster learning with global optimal solution can be achieved. A mathematical framework on the weight evolution of the new algorithm in also presented in this paper, which gives a careful analysis on the requirements of weight evolution (or perturbation) during learning in order to achieve a better error performance in the weights between different hidden layers. Simulation results on three typical problems including XOR, 3-bit parity and the counting problem are described to illustrate the fast learning behaviour and the global search capability of the new algorithm in improving the performance of back-propagated network.

We have made an exhaustive computation to establish that 33 comparisons never sort 13 items. The computation was carried out within 10 days by a workstation. Since merge insertion sort [Ford, et al. A tournament problem, Amer. Math. Monthly, vol. 66, (1959)] uses 34 comparisons for sorting 13 items, our result guarantees the optimality of the sorting procedure to sort 13 items as far as the number of comparisons is concerned. The problem has been open for nearly three decades since Mark Wells discovered that 30 comparisons are required to sort 12 items in 1965.

In this paper, we present Branching Oriented System Equation based on-line error correction scheme for recursive digital signal processing. The target digital signal processing is linear and time-invariant, and the algorithm includes multiplications with constant coefficient, additions and delays. The difficulties of the algorithm-level fault tolerance for such algorithm without structural regularity include error distribution problem and right timing of error correction. To escape the error distribution problem, multiple fan-out nodes in an algorithm are specified as the nodes at which error corrections are performed. The Branching Oriented Graph and Branching Oriented System Equation are so introduced to formulate on-line correction schemes based on this strategy. The Branching Oriented Graph is treated as the collection of computation sub-blocks. Applying checksum code independently to each sub-block is our most trivial on-line error correction scheme, and it results in, with appropriate selection of error identification process, TMR in sub-block level. One of the advantages of our method is in the reduction of redundant operations performed by merging some computation sub-blocks. On the other hand, the schedulability of the system is an important issue for our method since our on-line error correction mechanism induces additional data dependencies. In this paper, the schedulability condition and some modifications on the scheme are also discussed.

ACk is the class of problems solvable by an alternating Turing machine in space O(log n) and alternation depth O(logk n) [S. A. Cook, A taxonomy of problems with fast parallel algorithms, Inform. Contr. vol. 64]. We consider a game played by two persons: each player alternately moves a marker along an edge of a given digraph, and the first palyer who cannot move loses the game. It is shown that the problem to determine whether the first player can win the game on a digraph with n nodes exactly after logk n moves is complete for ACk nuder NC1 reducibility.

Real-time collision detection is one of the most important intelligent processings in robotics. In collision detection, a large storage capasity is usually required to store the 3-dimensional information on the obstacles located in a workspace. Moreover, high-computational power is essential in not only coordinate transformation but also matching operation. In the proposed collision detection VLSI processor, the matching operation is drastically accelerated by using a content-addressable memory (CAM). A new obstacle representation based on a union of rectangular solids is also used to reduce the obstacle memory capacity, so that the collision detection can be performed by only magnitude comparison in parallel. Parallel architecture using several identical processor elements (PEs) is employed to perform the coordinate transformation at high speed, and each PE performs coordinate transformation at high speed based on the COordinate Rotation DIgital Computation (CORDIC) algorithms. When the 16 PEs and 144-kb CAM are used, the performance is evaluated to be 90 ms.

This paper presents an overview of the SDC-I (Super Database Computer I) developed at the University of Tokyo, Japan. The purpose of the project was to build a high performance SQL server which emphasizes query processing over transaction processing. Recently relational database systems tend to be used for heavy decision support queries, which include many join, aggregation, and order-by operations. At present high-end mainframes are used for these applications requiring several hours in some cases. While the system architecture for high traffic transaction processing systems is well established, that for adhoc query processing has not yet adequately understood. SDC-I proved that a parallel machine could attain significant performance improvements over a coventional sequential machine through the exploitation of the high degree of parallelism present in relational query processing. A unique bucket spreading parallel hash join algorithm is employed in SDC, which makes the system very robust in the presense of data skew and allows SDC to attain almost linear performance scalability. SDC adopts a hybrid parallel architecture, where globally it is a shared nothing architecture, that is, modules are connected through the multistage network, but each module itself is a symmetric multiprocessor system. Although most of the hardware elements use commodity microprocessors for improved performance to cost, only the interconnection network incorporates the special function to support our parallel relational algorithm. Data movement over the memory and the network, rather than computation, is heavy for I/O intensive database processing. A dedicated software system was carefully designed for efficient data movement. The implemented prototype consists of two modules. Its hardware and software organization is described. The performance monitoring tool was developed to visualize the system activities, which showed that SDC-I works very efficiently.

A fast Newton/LMS algorithm is proposed which uses an efficient inversion technique of input autocorrelation matrix when the periodic pseudo random sequence is used as the reference signal. The number of operations is greatly reduced and the computational results show fast convergence rate and low misadjustment error. And the application of the algorithm to the case of nonperiodic reference signal is described.

We study robot navigation in unknown environment with rectangular obstacles aligned with the x and y axes. We propose a strategy called the modified-bian heuristic, and analyze its efficiency. Let n be the distance between the start point and the target of robot navigation, and let k be the maximum side length among the obstacles in a scene. We show that if k=(o(n) and if the summation of the widths of the obstacles on the line crossing the target and along the y axis is o(n), then ratio of the total distance walked by the robot to the shortest path length between the start point and the target is at most arbitrarily close to 1+k/2, as n grows. For the same restrictions as above on the sizes of the obstacles, the ratio is also at most arbitrarily close to 1+3/4n, as n grows, where is the summation of lengths of the obstacles in y axis direction.

An efficient algorithm is presented for solving nonlinear resistive networks. In this algorithm, the techniques of the piecewise-linear homotopy method are introduced to the Katzenelson algorithm, which is known to be globally convergent for a broad class of piecewise-linear resistive networks. The proposed algorithm has the following advantages over the original Katzenelson algorithm. First, it can be applied directly to nonlinear (not piecewise-linear) network equations. Secondly, it can find the accurate solutions of the nonlinear network equations with quadratic convergence. Therefore, accurate solutions can be computed efficiently without the piecewise-linear modeling process. The proposed algorithm is practically more advantageous than the piecewise-linear homotopy method because it is based on the Katzenelson algorithm that is very popular in circuit simulation and has been implemented on several circuit simulators.

An adaptive LMS filtering system is proposed for computing the Discrete Walsh Transform (DWT). The signal to be transformed serves as the 'desired signal' for the adaptive filter, while a set of periodic Walsh sequences serve as the input signal vector for the adaptive filter. The weights of the adaptive filter provide the DWT. The given approach is more efficient in terms of the required computations and memory locations compared with the direct approach. In contract with existing Fast DWT algorithm, the proposed solution provides more flexibility as far as the signal block length is concerned. In other words, the proposed approach is not restricted to a block length N to be of power 2.

This paper presents an algorithm for string searching in a character lattice. A character lattice, which is obtained through a character recognition process, is a general and flexible data structure that represents many hypothesized strings in a document image. In this paper, the authors propose a simple and efficient algorithm; it consists of a single loop of some set-operations and scans the character lattice only once. The authors also describe two actual implementations of the algorithm; one uses Bit-Arrays and the other a Trie. Owing to its bir parallelism, the Bit-Array approach is able to search for a single pattern faster than the Trie approach, and is easily extended to complex matchings such as an approximate one. It is suited for document retrieval systems that need to search for a keyword as fast as possible. A hashed compact version of the character lattice is also useful to increase the speed of the search for a single pattern. In contrast, the Trie approach is able to search for a large number of patterns simultaneously, and is suited for document understanding systems that need to extract words from the character lattice. The experimental results have shown that both approaches achieve high performance.

It is demonstrated that the enhancement in the functional capability of an elemental transistor is quite essential in developing human-like intelligent electronic systems. For this purpose we have introduced the concept of four-terminal devices. Four-terminal devices have an additional dimension in the degree of freedom in controlling currents as compared to the three-terminal devices like bipolar and MOS transistors. The importance of the four-terminal device concept is demonstrated taking the neuron MOS transistor (abbreviated as neuMOS or νMOS) and its circuit applications as examples. We have found that any Boolean functin can be realized by a two-stage configuratin of νMOS inverters. In addition, the variable threshold nature of the device allows us to build real-time reconfigurable logic circuits (no floating gate charging effect is involved in varying the threshold). Based on the principle, we have developed Soft-Hardware Logic Circuits and Real-Time Rule-Variable Data Matching Circuits. A winner-take-all circuit which finds the largest signal by hardware parallel processing has been also developed. The circuit is applied to building an associative memory which is different from Hopfield network in both principle and operation. The hardware algorithm in which binary, multivalue, and analog operations are merged at a very device level is quite essential to establish intelligent information processing systems based on highly flexible, real-time programmable hardwares realized by four-terminal devices.

An automatic zip code recognition system for Japanese mail is proposed in this paper. It is assumed that a zip code is composed of three numerals and requited to be written in a specified frame. In actual images, however, the three numerals sometimes extend outside the specified frame and are not clearly separated. Considering this situation, the authors devised a system with two stages, the segmentation stage and the recognition stage. The segmentation stage consists of five steps: setting and adjusting of initial areas for numeral images (figures), calculation of the center of gravity of each figure, search for the horizontal and vertical boundaries of each figure, determination of the final area for each figure, and normalization of the figure in each final area. In the recognition stage, the Localized Arc Pattern Method (Arc method) proposed by Yoshimura et al. (1991) is implemented hierarchically; that is, a simple Arc method is applied first to each figure and a more complex one is applied subsequently unless the figure is identified in the first step. In the recognition process, every figure is judged as a numeral or otherwise rejected. The proposed system was applied to a database provided by the Institute for Post and Telecommunications Policy (IPTP). The segmentation algorithm yielded an adequate result. The recognition algorithm yielded scores as high as 90.6% in correct recognition rate and 0.7% in error rate. The best score of the precision index (P-index) specified by the IPTP was as low as 15.7 for the above mentioned IPTP database, while the score for another IPTP database was 16.9.