Evolution programs have been shown to be very useful in a variety of search and optimization problems, however, until now, there has been little attempt to apply evolution programs to channel routing problem. In this paper, we present an exolution program and identify the key points which are essential to successfully applying evolution programs to channel routing problem. We also indicate how integrating heuristic information related to the problem under consideration helps in convergence on final solutions and illustrate the validity of out approach by providing experimental results obtained for the benchmark tests. compared with the optimal solutions.

We are concerned with a subclass of deterministic pushdown automata (dpda) called very simple dpda's, and present a new direct branching algorithm for checking the inclusion for a pair of languages accepted by these dpda's. As usual, we take the maximal thickness (i.e., the length of the shortest input strings that make each stack symbol go to empry) of all stack symbols into account as one parameter of the given dpda's. Then the worst-case time complexity of our algorithm is polynomial with respect to these parameters. Without considering the thickness, the complexity is single exponential in the description length of the given dpda's. As far as we are concerned with very simple dpda's, our algorithm is very simple and direct, and is faster and much better than the previously given algorithms for the inclusion problem of dpda's.

We propose a decoding algorithm for the t-EC/AUED code proposed by Böinck and Tiborg. The proposed algorithm also reveals some remarkable properties of the code.

This paper tends to analyze the trends of the research in logic synthesis. The first part is devoted to an expertise of the efficiency of factorization methods developed during the last decade and to the proposal of dedicated methods for complex logic blocks. The second part shows the importance of Binary Decision Diagrams as representation of Boolean functions. Their use in the technology mapping phase of multiplexor-based FPGAs in an industrial tool is taken as illustration.

A model for a large network with an unidirectional linear respone (ULR) is proposed in this letter. This deterministic system has powerful computing properties in very close correspondence with earlier stochastic model based on McCulloch-Pitts neurons and graded neuron model based on sigmoid input-output relation. The exclusive OR problems and other digital computation properties of the earlier models also are present in the ULR model. Furthermore, many analog and continuous signal processing can also be performed using the simple ULR neural network. Several examples of the ULR neural networks for analog and continuous signal processing are presented and show extemely promising results in terms of performance, density and potential for analog and continuous signal processing. An algorithm for the ULR neural network is also developed and used to train the ULR network for many digital and analog as well as continuous problems successfully.

A new Viterbi algorithm with adaptive path reduction method is presented. The proposed system consists of the pre-decoder and reduced path Virerbi decoder. The predecoder separates the mixed channel noise from the received sequence. The number of errors in the pre-decoded error sequence is counted and the path reduction is implemented by the number of errors in pre-decoded error sequence. The path reduction is implemented as a function of channel condition because the errors in the pre-decoded error sequence can be considered as the channel error sequence. Due to the reduction of the path, the number of ACS (add compare select) operations can be reduced, which occupies the dominant part in Viterbi decoding. The ACS reduction ratio for the proposed system achieves up to 30% for the case of (2, 1, 2) Ungerboeck code without degradation of the error performance.

A new arithmetic multiple-valued algebra with functional completeness is introduced. The algebra is called Neuro-Algebra for it has very similar formula and architecture to neural networks. Two canonical forms of multiple-valued functions of this Neuro-Algebra are presented. Since the arithmetic operations of the Neuro-Aglebra are basically a weighted-sum and a piecewise linear operations, their implementations are very simple and straightforward. Furthermore, the multiple-valued networks based on the Neuro-Algebra can be trained by the traditional back-propagation learning algorithm directly.

An adaptive multichannel IIR lattice predictor for k-step ahead prediction is constructed and the effectiveness of the proposed predictor is evaluated using digital simulations.

In this paper we propose an architecture and an algorithm for the parallel execution of OPS5 production systems. It is known that current OPS5 production system interpreters spend almost 90% of their execution time in the match step. Thus, in this paper we focus on the speedup of the match step. The match algorithm used in OPS5 is called Rete and the algorithm uses a special kind of a date-flow network compiled from the left hand sides of rules. To achieve the maximum degree of parallelism of a given OPS5 program by as few processors as possible, the proposed parallel machine uses loosely coupled multiprocessors. Parallel machines designed for fine-grain parallelism, such as DADO, also use loosely coupled multiprocessors. However, the proposed machine differs from such machines at the following points: use of powerful processors which have large amounts of memories and small cycle times; use of a shared Rete network (parallel machines designed for fine-grain parallelism use an unshared Rete network); high hardware utilization. Basic ideas of the proposed parallel machine are as follows. (1) Use of a modified Rete network in which node sharing is used only for constant-test nodes and each memory node is lumped with the child two-input node. (2) Static allocation of the nodes of the modified Rete network onto processors. (3) Partition of the set of processors into three subsets: constant-test node processors, two-input node processors and conflict-set processors. (4) Use of a ring network for the interconnection network among two-input node processors. In addition to an architecture for parallel execution of OPS5 production systems, we propose a scheme for mapping the modified Rete network into the proposed architecture. The results of simulation experiments showed that the proposed architecture is promising for parallel execution of OPS5 production systems.

A hardware algorithm for modular inversion is proposed. It is based on the extended Euclidean algorithm. All intermediate results are represented in a redundant binary representation with a digit set {0, 1,1}. All addition/subtractions are performed without carry propagation. A modular inversion is carried out in O (n) clock cycles where n is the word length of the modulus. The length of each clock cycle is constant independent of n. A modular inverter based on the algorithm has a regular cellular array structure with a bit slice feature and is very suitable for VLSI implementation. Its amount of hardware is proportional to n.

Properties of a strongly-coupled nonlinear directional coupler (NLDC) with a lossy MQW coupling layer is analyzed using the Galerkin finite element method accompanied by a predictor-corrector algorithm. It is shown that the propagation attenuation along the NLDC is considerably smaller than that in the bulk MQW and tends to reduce with the input power. By the presence of losses, the powers guided in two waveguides do not become a maximum and a minimum at the same propagation length, unlike the lossless coupler. The losses make the nonlinear effect weak due to the decrease in guided power, and hence the coupling length decreases and the switching power increases. The extinction ratio of the switching becomes the largest value not in the cases of nonloss and high losses but in the case of moderately high losses, although the switching power is somewhat larger than that of the lossless case.

This paper presents a new redundant fault identification algorithm, REDUCT. This algorithm handles the redundant fault identification problem by transforming a given circuit into another circuit. It also reduces the complexity of the transformed circuit, which is caused by a large number of reconvergences and head lines, using five circuit reduction techniques. Further, it proves redundancies and generates test patterns for hard faults more efficiently than conventional test pattern generation algorithms. We obtained 100% fault coverage for all ISCAS85 benchmark circuits using REDUCT following the execution of the test pattern generation algorithm N2-V.

This letter presents a new algorithm for echo cancellers, which prevents the reduction of echo return loss due to a double-talk. The essence of the algorithm is to introduce signal delays to avoid the reduction. A convergence condition in the algorithm was examined by using the IIR filter expression of the NLMS algorithm, and it was concluded that the IIR filter should be a low pass filter with unity gain. The condition is accomplished by selecting a small step gain.

A new neural network system for object recognition is proposed which is invariant to translation, scaling and rotation. The system consists of two parts. The first is a preprocessor which obtains projection from the input image plane such that the projection features are translation and scale invariant, and then adopts the Rapid Transform which makes the transformed outputs rotation invariant. The second part is a neural net classifier which receives the outputs of preprocessing part as the input signals. The most attractive feature of this system is that, by using only a simple shift invariant transformation (Rapid transformation) in conjunction with the projection of the input image plane, invariancy is achieved and the system is of reasonably small size. Experiments with six geometrical objects with different degrees of scaling and rotation shows that the proposed system performs excellent when the neural net classifier is trained by the Cascade-correlation learning algorithm proposed by Fahlman and Lebiere.

A laser system which has a mirror outside of it to feedback a delayed output has been described by the Maxwell-Bloch equations with time delay. It is shown that a chaotic behavior in the equations can be controlled by using a OPF control algorithm. Our numerical simulation indicates that the chaotic behavior is stabilized on 1, 2 periodic unstable orbits.

An estimation method of region is presented, in which a solution path of the so-called Newton type homotopy equation in guaranteed to exist, it is applied to a certain class of uniquely solvable nonlinear equations. The region can be estimated a posteriori, and its upper bound also can be estimated a priori.

This paper presents efficient algorithms for finding the largest tree S such that there are vertex disjoint subtrees S1, , S (k1) of T each of which is isomorphic to S and every leaf of T is a leaf of some Si. The algorithms are useful for learning a macro table.

A superresolution technique is considered for use in antenna gain measurements. A modification of the MUSIC algorithm is employed to resolve incident signals separately in the time domain. The modification involves preprocessing the received data using a spatial scheme prior to applying the MUSIC algorithm. Interference rejection in the antenna measurements using the fast Fourier transform (FFT) based techniques have been realized by a recently developed vector network analyzer, and its availability has been reported in the literature. However, response resolution in the time domain of these conventional techniques is limited by the antenna bandwidth. The MUSIC algorithm has the advantage of being able to eliminate unwanted responses when performing antenna measurements in situations where the antenna band-width is too narrow to support FFT based techniques. In this paper, experimental results of antenna gain measurements in a multipath environment show the accuracy and resolving power of this technique.

In this paper, we discuss to the intermedia synchronization problems for high speed multimedia communication. Especially, we described how software synchronization can be operated, and estimated the skew bound in CNV when considering the network delay. And we applied CNV to the intermedia synchronization and a hybrid model (HSM) is proposed. Furthermore, we used the statistical approach to evaluate the performance of the synchronization mechanisms. The results of performance evaluation show that HSM has good performance in the probability of estimation error.

The most commonly used activation function in Backpropagation learning is sigmoidal while linear function is also sometimes used at the output layer with the view that choice between these activation functions does not make considerable differences in network's performance. In this letter, we show distinct performance between a network with linear output units and a similar network with sigmoid output units in terms of convergence behavior and generalization ability. We experimented with two types of cost functions, namely, sum-squared error used in standard Backpropagation and log-likelihood recently reported. We find that, with sum-squared error cost function and hidden units with nonsteep sigmoid function, use of linear units at the output layer instead of sigmoidal ones accelerates the convergence speed considerably while generalization ability is slightly degraded. Network with sigmoid output units trained by log-likelihood cost function yields even faster convergence and better generalization but does not converge at all with linear output units. It is also shown that a network with linear output units needs more hidden units for convergence.