Hyperthermia is one of the modalities for cancer treatment, utilizing the difference of thermal sensitivity between tumor and normal tissue. Interstitial microwave hyperthermia is one of the heating schemes and it is applied to a localized tumor. In the treatments, heating pattern control around antennas are important, especially for the treatment in and around critical organs. This paper introduces a coaxial-dipole antenna, which is one of the thin microwave antennas and can generate a controllable heating pattern. Moreover, generations of an arbitrary shape heating patterns by an array applicator composed of four coaxial-dipole antennas are described.

In the image classification applications, the test sample with multiple man-handcrafted descriptions can be sparsely represented by a few training subjects. Our paper is motivated by the success of multi-task joint sparse representation (MTJSR), and considers that the different modalities of features not only have the constraint of joint sparsity across different tasks, but also have the constraint of local manifold structure across different features. We introduce the constraint of local manifold structure into the MTJSR framework, and propose the Locality-constrained multi-task joint sparse representation method (LC-MTJSR). During the optimization of the formulated objective, the stochastic gradient descent method is used to guarantee fast convergence rate, which is essential for large-scale image categorization. Experiments on several challenging object classification datasets show that our proposed algorithm is better than the MTJSR, and is competitive with the state-of-the-art multiple kernel learning methods.

This paper proposes an enhancement to a previously reported adaptive peak-to-average power ratio (PAPR) reduction method based on clipping and filtering (CF) for eigenmode multiple-input multiple-output (MIMO) — orthogonal frequency division multiplexing (OFDM) signals. We enhance the method to accommodate the case with adaptive modulation and channel coding (AMC). Since the PAPR reduction process degrades the signal-to-interference and noise power ratio (SINR), the AMC should take into account this degradation before PAPR reduction to select accurately the modulation scheme and coding rate (MCS) for each spatial stream. We use the lookup table-based prediction of SINR after PAPR reduction, in which the interference caused by the PAPR reduction is obtained as a function of the stream index, frequency block index, clipping threshold for PAPR reduction, and input backoff (IBO) of the power amplifier. Simulation results show that the proposed PAPR reduction method increases the average throughput compared to the conventional CF method for a given adjacent channel leakage power ratio (ACLR) when we assume practical AMC.

A coarse-grained reconfigurable architecture (CGRA) is typically hybrid architecture, which is composed of a reconfigurable processing unit (RPU) and a host microprocessor. Many computation-intensive kernels (e.g., loop nests) are often mapped onto RPUs to speed up the execution of programs. Thus, mapping optimization of loop nests is very important to improve the performance of CGRA. Processing element (PE) utilization rate, communication volume and reconfiguration cost are three crucial factors for the performance of RPUs. Loop transformations can affect these three performance influencing factors greatly, and would be of much significance when mapping loops onto RPUs. In this paper, a joint loop transformation approach for RPUs is proposed, where the PE utilization rate, communication cost and reconfiguration cost are under a joint consideration. Our approach could be integrated into compilers for CGRAs to improve the operating performance. Compared with the communication-minimal approach, experimental results show that our scheme can improve 5.8% and 13.6% of execution time on motion estimation (ME) and partial differential equation (PDE) solvers kernels, respectively. Also, run-time complexity is acceptable for the practical cases.

Comparable Corpora are valuable resources for many NLP applications, and extensive research has been done on information mining based on comparable corpora in recent years. While there are not enough large-scale available public comparable corpora at present, this paper presents a bi-directional CLIR-based method for creating comparable corpora from two independent news collections in different languages. The original Chinese document collections and English documents collections are crawled from XinHuaNet respectively and formatted in a consistent manner. For each document from the two collections, the best query keywords are extracted to represent the essential content of the document, and then the keywords are translated into the language of the other collection. The translated queries are run against the collection in the same language to pick up the candidate documents in the other language and candidates are aligned based on their publication dates and the similarity scores. Results show that our approach significantly outperforms previous approaches to the construction of Chinese-English comparable corpora.

For source camera identification, we propose a method to reconstruct the sensor pattern noise map from a size-reduced query image by minimizing an objective function derived from the observation model. Our method can be applied to multiple queries, and can thus be further improved. Experiments demonstrate the superiority of the proposed method over conventional interpolation-based magnification algorithms.

To decrease memory access of the decoder for double binary convolutional turbo code (DB CTC), an iterative decoding scheme is proposed. Instead of accessing all of the backward state metrics from the state metric cache (SMC), a part of them is computed by the recalculation unit (RU) in the forward direction. By analysis and simulations, both the amount of memory access and the size of SMC are reduced by about 45%. Moreover, combined with the scaling technique, the proposed scheme gets decoding performance near to that of the well-known Log-MAP algorithm.

This paper studies the simple dynamic binary neural network characterized by the signum activation function, ternary weighting parameters and integer threshold parameters. The network can be regarded as a digital version of the recurrent neural network and can output a variety of binary periodic orbits. The network dynamics can be simplified into a return map, from a set of lattice points, to itself. In order to store a desired periodic orbit, we present two learning algorithms based on the correlation learning and the genetic algorithm. The algorithms are applied to three examples: a periodic orbit corresponding to the switching signal of the dc-ac inverter and artificial periodic orbit. Using the return map, we have investigated the storage of the periodic orbits and stability of the stored periodic orbits.

This letter studies a digital return map that is a mapping from a set of lattice points to itself. The digital map can exhibit various periodic orbits. As a typical example, we present the digital logistic map based on the logistic map. Two fundamental results are shown. When the logistic map has a unique periodic orbit, the digital map can have plural periodic orbits. When the logistic map has an unstable period-3 orbit that causes chaos, the digital map can have a stable period-3 orbit with various domain of attractions.

Aiming to alleviate the visual tracking problem of drift which reduces the abilities of almost all online visual trackers, a robust visual tracker (called CCMM tracker) is proposed with a coupled-classifier based on multiple representative appearance models. The coupled-classifier consists of root and head classifiers based on local sparse representation. The two classifiers collaborate to fulfil a tracking task within the Bayesian-based tracking framework, also to update their templates with a novel mechanism which tries to guarantee an update operation along the “right” orientation. Consequently, the tracker is more powerful in anti-interference. Meanwhile the multiple representative appearance models maintain features of the different submanifolds of the target appearance, which the target exhibited previously. The multiple models cooperatively support the coupled-classifier to recognize the target in challenging cases (such as persistent disturbance, vast change of appearance, and recovery from occlusion) with an effective strategy. The novel tracker proposed in this paper, by explicit inference, can reduce drift and handle frequent and drastic appearance variation of the target with cluttered background, which is demonstrated by the extensive experiments.

Apriori-based mining algorithms enumerate frequent patterns efficiently, but the resulting large number of patterns makes it difficult to directly apply subsequent learning tasks. Recently, efficient iterative methods are proposed for mining discriminative patterns for classification and regression. These methods iteratively execute discriminative pattern mining algorithm and update example weights to emphasize on examples which received large errors in the previous iteration. In this paper, we study a family of loss functions that induces sparsity on example weights. Most of the resulting example weights become zeros, so we can eliminate those examples from discriminative pattern mining, leading to a significant decrease in search space and time. In computational experiments we compare and evaluate various loss functions in terms of the amount of sparsity induced and resulting speed-up obtained.

Data encryption and decryption are common operations in network-based application programs that must offer security. In order to keep pace with the high data input rate of network-based applications such as the multimedia data streaming, real-time processing of the data encryption/decryption is crucial. In this paper, we propose a new parallelization approach to improve the throughput performance for the de-facto standard data encryption and decryption algorithm, AES-CTR (Counter mode of AES). The new approach extends the size of the block encrypted at one time across the unit block boundaries, thus effectively encrypting multiple unit blocks at the same time. This reduces the associated parallelization overheads such as the number of procedure calls, the scheduling and the synchronizations compared with previous approaches. Therefore, this leads to significant throughput performance improvements on a computing platform with a general-purpose multi-core processor and a Graphic Processing Unit (GPU).

Content addressable memory is widely used for fast lookup table data searching, but it often consumes considerable power. Moreover, designing the suitable content addressable memory architecture for a specific application also consumes lots of time, since the behavioral simulation is often done in the transistor level. SystemC is a system-level modeling language and simulation platform, providing high simulation efficiency for hardware software co-design. Unfortunately, SystemC does not provide the function for estimating power dissipation of a structure design. In this paper, a SystemC-based fast content addressable memory power estimation method is presented for estimating the power dissipation of the match-line circuit, the search-line circuit, and the storage cell array of content addressable memory in the early design stage. The mathematical equations and behavioral patterns are used as the inputs of power estimation model. The simulation results based on 10 Mibench benchmarks show that the simulation time of the proposed method is in average 1233 times faster than that of HSPICE simulator with only 3.51% error rate.

MLPDA (Maximum Likelihood Probabilistic Data Association) has attracted a great deal of attention as an effective target track extraction method in high false density environments. However, to extract an accelerated target track on a 2-dimensional plane, the computational load of the conventional MLPDA is extremely high, since it needs to search for the most-likely position, velocity and acceleration of the target in 6-dimensional space. In this paper, we propose VG-MLPDA (Variable Gating MLPDA), which consists of the following two steps. The first step is to search the target's position and velocity among candidates with the assumed acceleration by using variable gates, which take into account both the observation noise and the difference between assumed and true acceleration. The second step is to search the most-likely position, velocity and acceleration using a maximization algorithm while reducing the gate volume. Simulation results show the validity of our method.

To provide robust wireless data transmission over fading channels, various schemes which involve the use of relays have been proposed. In some of those schemes, the relay chooses not to forward the received message if its reliability is deemed as too low. Some researchers refer to such schemes as selective decode-and-forward. Our work in this paper falls into such a category. More specifically speaking, the relay in our system is a censorial relay (a relay that performs censorial task). It evaluates the reliability, in terms of log likelihood ratio (LLR), of a received data bit (from the source). If its LLR magnitude is below some preset threshold, then it is censored (i.e. not sent to the destination). When the channel is Rayleigh faded, closed-form bit error rate (BER) expressions for the proposed system are derived for several scenarios. Those scenarios are differentiated by the availability of an energy detector (ED) and the various degrees of knowledge regarding the channel state information (CSI). Aided by those closed-form BER expressions, the system parameters can be efficiently optimized to achieve the minimum BER. Simulation results are observed to closely match theoretical values, as computed by the afore-mentioned closed-form BER expressions. As compared to some existing relay-assisted systems in which censoring is incorporated, the performance of our system is better in terms of BER when the same amount of CSI is exploited.

A complete 4-level pulse amplitude modulation (4-PAM) serial link transceiver including a wide frequency range clock generator and clock data recovery (CDR) is proposed in this paper. A dual-loop architecture, consisting of a frequency locked loop (FLL) and a phase locked loop (PLL), is employed for the wide frequency range clocks. The generated clocks from the FLL (clock generator) and the PLL (CDR) are utilized for a transmitter clock and a receiver clock, respectively. Both FLL and PLL employ the identical voltage controlled oscillators consisting of ring-type delay-cells. To improve the frequency tuning range of the VCO, deep triode PMOS loads are utilized for each delay-cell, since the turn-on resistance of the deep triode PMOS varies substantially by the gate-voltage. As a result, fabricated in a 0.13-µm CMOS process, the proposed 4-PAM transceiver operates from 1.5 Gb/s to 9.7 Gb/s with a bit error rate of 10-12. At the maximum data-rate, the entire power dissipation of the transceiver is 254 mW, and the measured jitter of the recovered clock is 1.61 psrms.

Petri nets are a kind of formal language that are widely applied in concurrent systems associated with resource allocation due to their abilities of the natural description on resource allocation and the precise characterization on deadlock. Weighted System of Simple Sequential Processes with Resources (WS3PR) is an important subclass of Petri nets that can model many resource allocation systems in which 1) multiple processes may run in parallel and 2) each execution step of each process may use multiple units from a single resource type but cannot use multiple resource types. We first prove that the liveness problem of WS3PR is co-NP-hard on the basis of the partition problem. Furthermore, we present a necessary and sufficient condition for the liveness of WS3PR based on two new concepts called Structurally Circular Wait (SCW) and Blocking Marking (BM), i.e., a WS3PR is live iff each SCW has no BM. A sufficient condition is also proposed to guarantee that an SCW has no BM. Additionally, we show some advantages of using SCW to analyze the deadlock problem compared to other siphon-based ones, and discuss the relation between SCW and siphon. These results are valuable to the further research on the deadlock prevention or avoidance for WS3PR.

In order to execute coherent Doppler processing in a high range-rate scenario, whether it is for detection, estimation or imaging, range walk embedded in target return should be compensated first. In case of a bistatic radar geometry where a transmitter, a receiver and a target can be all moving, the extent of range walk depends on their relative positions and velocities. This paper presents a coherent Doppler processing algorithm to achieve target detection and Doppler frequency estimation of a target under a bistatic radar geometry. This algorithm is based on the assumption that a target has constant Doppler frequency during a coherent processing interval (CPI). Thus, we first show under what condition the assumption could be valid. We next develop an algorithm, along with its implementation procedures where the region of range walk, called a window, is manipulated. Finally, the performance of a proposed algorithm is examined through simulations.

This paper proposes a method for evaluating visual differences caused by decimation. In many applications it is important to evaluate visual differences of two different images. There exist many image assessment methods that utilize the model of the human visual system (HVS), such as the visual difference predictor (VDP) and the Sarnoff visual discrimination model. In this paper, we extend and elaborate on the conventional image assessment method for the purpose of evaluating the visual difference caused by the image decimation. Our method matches actual human evaluation more and requires less computational complexity than the conventional method.

In the next generation mobile network, the demand for high data rate transmission will require an increase in the transmission power if the current mobile cellular network architecture is used. Multihop networks are considered to be a key solution to this problem. However, a new resource allocation algorithm is also required for the new network architecture. In this paper, we propose a resource allocation scheme for a parallel relay 2-hop OFDMA virtual cellular network (VCN) which can be applied in a multiuser environment. We evaluate, by computer simulation, the ergodic channel capacity of the VCN using the proposed algorithm, and compare the results with those of the conventional single hop network (SHN). In addition, we analyze the effect of the location of the relay wireless ports on the ergodic channel capacity of the VCN. We also study the degree of fairness of the VCN, using the proposed scheme, compared with that of the SHN. For low transmission power, the simulation results show: a) the VCN can provide a better ergodic channel capacity and a better degree of fairness than the SHN, b) the distance ratio for which the ergodic channel capacity of the VCN is maximal can be found in the interval 0.20.3, c) the ergodic channel capacity of the VCN remains better than that of the SHN as the number of users increases, and d) as the distance between the relay WPs and the base station increases, the channel capacity of VCN approaches that of the SHN.