A well-defined test structure of organic static-induction transistor (SIT) having regularly sized nano-apertures in the gate electrode has been fabricated by colloidal lithography using 130-nm-diameter polystyrene spheres as shadow masks during vacuum deposition. Transistor characteristics of individual nano-apertures, namely 'nano-SIT,' have been measured using a conductive atomic-force-microscope (AFM) probe as a movable source electrode. Position of the source electrode is found to be more important to increase current on/off ratio than the distance between source and gate electrodes. Experimentally obtained maximum on/off ratio was 710 (at VDS = -4 V, VGS = 0 and 2 V) when a source electrode was fixed at the edge of gate aperture. The characteristics have been then analyzed using semiconductor device simulation by employing a strongly non-linear carrier mobility model in the CuPc layer. From device simulation, source current is found to be modulated not only by a saddle point potential in the gate aperture area but also by a pinch-off effect near the source electrode. According to the obtained results, a modified structure of organic SIT and an adequate acceptor concentration is proposed. On/off ratio of the modified organic SIT is expected to be 100 times larger than that of a conventional one.

As VLSI technology advances, delay variations will become more serious. Delay-insensitive asynchronous dual-rail circuits tolerate any delay variation, but their energy consumption is more than double that of the single-rail circuits because signal transitions occur every cycle in all bits regardless of the input bit pattern. However, in functional units, a significant number of input bits may not change from the previous input in many cases. In such a situation, calculation of these bits is not required. Thus, we propose a method, called unflip-bits control, makes use of the above situation, to reduce energy consumption. We evaluate the energy consumption and performance penalty for the method using HSPICE and the verilog-XL simulator, and compare the method with the conventional dual-rail circuit and a synchronous circuit. Our evaluation results reveal that the proposed asynchronous dual-rail circuit has a 12-60% lower energy consumption compared with a conventional asynchronous dual-rail circuit.

Radio frequency identification (RFID) technology is becoming increasingly attractive because of its high storage capacity and reprogrammability. There is a challenge to be overcome when a reader needs to read a number of tags within the reader's interrogation zone at the same time. In this paper, we present an anti-collision scheme in a RFID system. The scheme is based on the dynamic framed ALOHA protocol developed for radio networks. In our scheme, we propose two methods to estimate the number of tags. Simulation results indicate that the total number of time slots for reading all tags is about 4 times the number of tags that need to be read, including acknowledgement time slots. The main advantages of our scheme are the great performance of uplink throughput and its easy implementation for both readers and tags.

This letter presents an efficient Signed-Power-of-Two (SPT) term allocation for filter coefficients in order to improve the BER characteristics of digital communication systems. The performance of the present allocation is evaluated by BER characteristics through digital modulation simulations and FPGA-based digital implementation.

A new transmission line structure is presented in this work for advanced CMOS processes. This structure has a high quality factor and low attenuation. It allows slow-waves to propagate which results in low dispersion for a given characteristic impedance. It is also designed to satisfy the stringent density requirements of advanced CMOS processes. A model is developed to characterize this structure by analyzing the physical current flowing in the substrate and the shield structure. Test structures were fabricated using CMOS 90 nm process technology with measurements made up to 110 GHz using a transmission-reflection module on a network analyzer. The results correspond well to the proposed model.

Dynamically reconfigurable processors are consisting of an array of processing elements whose functions and interconnections can be dynamically changed. 9 commercial systems are picked up, and their array structures, processing elements and interconnection architectures are classified.

In this letter, we focus on non-pilot-symbol assisted integer frequency offset estimation for multicarrier orthogonal frequency division multiplexing (OFDM) systems. We introduce a frequency offset estimator that is based on the guard interval (GI) present in OFDM signals. We show by simulation that the frequency offset estimator can accurately estimate the frequency misalignment at the sacrifice of limited estimation range.

This paper presents a hardware-efficient folding technique for high-order FIR filtering while considering the tradeoff between the number of processing elements and throughput rate. Given the throughput rate, one can always employ the minimum number of processing elements for saving the implementation cost and figure out a folded architecture. However, applying inefficient folding techniques may result in costly switches and registers. Therefore, our work intends to evaluate the efficiency for folding techniques in terms of the number of registers, and the power dissipation of registers. As shown in the estimation results, while comparing with the published folded architectures under the same throughput rate, the proposed folding technique can turn out less power dissipation and low hardware complexity than the others. The proposed design has been implemented using TSMC 0.18 µm 1P6M technology. As seen in the post-layout simulation, our design can meet the requirement of IS-95 WCDMA pulse shaping FIR filter while the power consumption can be as low as 16.66 mW.

One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In MTCMOS circuit, voltage on virtual ground fluctuates due to a discharge current of a logic cell. This event affects to the cell delay and makes static timing analysis (STA) difficult. In this paper, we propose a delay modeling and static STA methodology targeting at MTCMOS circuits. In the proposed method, we prepare a delay look-up table (LUT) consisting of the input slew, the output load capacitance, the virtual ground length, and a power-switch size. Using this LUT, we compute a circuit delay for each logic cell by applying the linear interpolation. This technique enables to calculate the cell delay considering the delay increase by the voltage fluctuation of virtual ground line. Experimental results show that the proposed methodology enables to estimate the cell delay and the critical path delay within 8% errors compared with SPICE simulation.

This paper represents a cycle-based logic simulation method using an LUT cascade emulator, where an LUT cascade consists of multiple-output LUTs (cells) connected in series. The LUT cascade emulator is an architecture that emulates LUT cascades. It has a control part, a memory for logic, and registers. It connects the memory to registers through a programmable interconnection circuit, and evaluates the given circuit stored in the memory. The LUT cascade emulator runs on an ordinary PC. This paper also compares the method with a Levelized Compiled Code (LCC) simulator and a simulator using a Quasi-Reduced Multi-valued Decision Diagram (QRMDD). Our simulator is 3.5 to 10.6 times faster than the LCC, and 1.1 to 3.9 times faster than the one using a QRMDD. The simulation setup time is 2.0 to 9.8 times shorter than the LCC. The necessary amount of memory is 1/1.8 to 1/5.5 of the one using a QRMDD.

This letter proposes a novel approach for mel-cepstral analysis based on the psychoacoustic model of MPEG. A perceptual weighting function is developed by applying cubic spline interpolation on the signal-to-mask ratios (SMRs) which are obtained from the psychoacoustic model. Experiments on speaker identification and speech re-synthesis showed that the proposed method not only improved the speaker recognition performance, but also improved the speech quality of the re-synthesized speech.

Molecular aligned naphthacene thins films were fabricated using vacuum evaporation and the rubbing method. The attenuated total reflection (ATR) and emission light properties from surface plasmon (SP) excitation due to molecular luminescence were investigated for these films. The long axis of the rod-like molecule was estimated to align perpendicular to the rubbing direction. The ATR and emission light properties depended on the molecular orientation.

This paper considers the optimal generator matrices of a given binary cyclic code over a binary symmetric channel with crossover probability p→0 when the goal is to minimize the probability of an information bit error. A given code has many encoder realizations and the information bit error probability is a function of this realization. Our goal here is to seek the optimal realization of encoding functions by taking advantage of the structure of the codes, and to derive the probability of information bit error when possible. We derive some sufficient conditions for a binary cyclic code to have systematic optimal generator matrices under bounded distance decoding and determine many cyclic codes with such properties. We also present some binary cyclic codes whose optimal generator matrices are non-systematic under complete decoding.

Organic field-effect transistors (OFETs) based on a composite with the same thiophene backbone were fabricated by spin coating using an annealing solution of poly(3-hexylthiophene) (PAT6) and α, ω-dihexylsexithiophene (DH-6T). The morphology of grains on the non-octadecyltrichlorosilane (OTS) treated and OTS treated gate insulators is granular and tube-like, respectively. The different morphologies of the OFETs with non-OTS treated and OTS-treated gate insulators result in the improvement of field-effect mobility. In the case of poly(ethylene naphthalate) substrate, an OFET with an 89 wt% DH-6T composite corresponding to two molecules of DH-6T per hexylthiophene repeating unit had a carrier mobility of 0.019 cm2/Vs.

We demonstrate single electron counting on an alkanethiol-protected Au nanodot in a double-barrier tunneling structure by noncontact atomic-force spectroscopy (nc-AFS). The Coulomb step width dependence on the Au nanodot diameter is observed. Evaluation of fractional charge Q0 and contact potential difference by nc-AFS reveals a Vd-independent voltage shift due to Q0.

Frequency-variation method (FVM), reported in [1], was further studied for simultaneously measuring the both complex permittivity and complex permeability by intentionally changing the test frequency to obtain different reflections. An enhanced coaxial-probe-based in-situ measurement system has been established. The spectral domain full-wave model is derived to take place of the quasi-static one. A novel coaxial probe is designed so that the one-port calibration could be performed with Agilent-supplied precise cal-kit instead of the liquid standard. Criterions for a right order of the interpolation polynomial used to approximate the frequency-dependent EM parameters; measures to reduce the residual mismatch errors and random error in reflection measurements and to suppress the ambiguities in solving the transcendent equation system were experimentally studied to resolve the problems and improve the accuracy in dispersive absorbing materials' test. Several typical dispersive absorbing coatings have been tested via FVM. The good comparison between the measured results and reference ones validate the feasibility of the proposed improved technique.

Set Partitioning in Hierarchical Trees (SPIHT) is a highly efficient technique for compressing Discrete Wavelet Transform (DWT) decomposed images. Though its compression efficiency is a little less famous than Embedded Block Coding with Optimized Truncation (EBCOT) adopted by JPEG2000, SPIHT has a straight forward coding procedure and requires no tables. These make SPIHT a more appropriate algorithm for lower cost hardware implementation. In this paper, a modified SPIHT algorithm is presented. The modifications include a simplification of coefficient scanning process, a 1-D addressing method instead of the original 2-D arrangement of wavelet coefficients, and a fixed memory allocation for the data lists instead of a dynamic allocation approach required in the original SPIHT. Although the distortion is slightly increased, it facilitates an extremely fast throughput and easier hardware implementation. The VLSI implementation demonstrates that the proposed design can encode a CIF (352288) 4:2:0 image sequence with at least 30 frames per second at 100-MHz working frequency.

Sequence set with Three Zero Correlation Zones (T-ZCZ) is applied in Quasi-Synchronized CDMA communication system to reduce the Multiple Access Interference (MAI) and Inter Symbol Interference (ISI). In this letter, we present a class of sequence set with Three Low Correlation Zones (T-LCZ), which has more sequences and flexibility than T-ZCZ sequence set. Moreover, the theoretical bound on T-LCZ sequences is derived for estimating the performance of such sequence set.

Combinatorial designs have been used to construct digital fingerprint codes. Here, a new constructive algorithm for an anticollusion fingerprint code based on group-divisible designs is presented. These codes are easy to construct and available for a large number of individuals, which is important from a business point of view. Group-divisible designs have not been used previously as a tool for fingerprint code construction.

We previously proposed an architecture for software defined radio called the reconfigurable packet routing-oriented signal processing platform (RPPP). This architecture was suited to wireless signal processing applications, which require radio functions to be selected in real time depending on the transmitted signal. A number of radio standards are used in DSRC systems for vehicle communication and vehicle equipment is required to transmit and receive the radio signals used on each particular occasion. An implementation of RPPP is described in this paper that enables the dynamic handling of two ARIB standards for DSRC. After an explanation of the basic architecture and an analysis of RPPP, the implementation of a reconfigurable DSRC transceiver for ASK and π/4 shift-QPSK is described. The implementation is then discussed, evaluated in terms of the number of logic units needed. We concluded that our platform is 27.6% more efficient in utilizing logic than that achieved with fixed design.