This paper presents the design, fabrication and characterization of a low actuation voltage capacitive shunt RF-MEMS switch for microwave and millimeter-wave applications based on a corrugated electrostatic actuated bridge suspended over a concave structure of coplanar waveguide (CPW), with sputtered nickel as the structural material for the bridge and gold for CPW line, fabricated on high-resistivity silicon (HRS) substrate using IC compatible processes for modular integration in a communication devices. The residual stress is very low because having both ends corrugated structure of the bridge in concave structure. The residual stress is calculated about 3-15 MPa in corrugated bridge and 30 MPa in flat bridge. The corrugated bridge of the concave structure requires lower actuation voltages 20-80 V than 50-100 V of the flat bridge of the planar structure in 0.3 to 1.0 µm thick Ni capacitive shunt RF-MEMS switch, in insertion loss 1.0 dB, return loss 12 dB, power loss 10 dB and isolation 28 dB from 0.5 up to 40 GHz. The residual stress of the bridge material and structure is critical to lower the actuation voltage.

A novel sensing system for glucose in aqueous solution based on cataluminescence(CTL) is proposed. CTL is a kind of chemiluminescence emitted in a course of catalytic oxidation of combustible substances. A sensing system consisting of a CTL-based chemical-sensor made of the γ-Al2O3 catalyst activated with Tb and an ultrasonic nebulizer is developed. CTL is emitted by injection of air containing mist of a glucose solution prepared by the nebulizer on the catalyst. The CTL intensity measured by a photomultiplier is reproducible for the repeated injection of the mist, and the system can measure glucose concentration in a range of 1-200 mg/dl.

In this letter, efficient two-dimensional (2-D) fast algorithms for realizations of 88 forward and inverse integer transforms in H.264/AVC fidelity range extensions (FRExt) are proposed. Based on matrix factorizations with Kronecker product and direct sum operations, efficient fast 2-D 88 forward and inverse integer transforms can be derived from the one-dimensional (1-D) fast 88 forward and inverse integer transforms through matrix operations. The proposed fast 2-D 88 forward and inverse integer transform designs don't require transpose memory in hardware realizations. The fast 2-D 88 integer transforms require fewer latency delays and provide a larger throughput rate than the row-column based method. With regular modularity, the proposed fast algorithms are suitable for VLSI implementations to achieve H.264/AVC FRExt high-profile signal processing.

In a partially reconfigurable FPGA of the future, arbitrary portions of its logic resources and interconnection networks will be reconfigured without affecting the other parts. Multiple tasks will be mapped and executed concurrently in such an FPGA. Efficient execution of the tasks using the limited resources of the FPGA will necessitate effective resource management. A number of online FPGA placement methods have recently been proposed for such an FPGA. However, they cannot handle I/O communications of the tasks. Taking such I/O communications into consideration, we introduce a new approach to online FPGA placement. We present an algorithm for placing each arriving task in an empty area so as to complete all the tasks efficiently. We develop two fitting strategies to effectively handle I/O communications of the tasks. Our experimental results show that properly weighted combinations of these and two other previously proposed strategies enable this algorithm to run very fast and make an effective placement of the tasks. In fact, we show that the overhead associated with the use of this algorithm is negligible as compared to the total execution time of the tasks.

We propose an elastic pipeline that can apply dynamic voltage scaling (DVS) to hardwired logic circuits. In order to demonstrate its feasibility, a hardwired H.264/AVC HDTV decoder is designed as a real-time application. An entropy decoding process is divided into context-based adaptive binary arithmetic coding (CABAC) and syntax element decoding (SED), which has advantages of smoothing workload for CABAC and keeping efficiency of the elastic pipeline. An operating frequency and supply voltage are dynamically modulated every slot depending on workload of H.264 decoding to minimize power. We optimize the number of slots per frame to enhance power reduction. The proposed decoder achieves a power reduction of 50% in a 90-nm process technology, compared to the conventional clock-gating scheme.

In this letter, we focus on non-pilot-symbol assisted integer frequency offset estimation for multicarrier orthogonal frequency division multiplexing (OFDM) systems. We introduce a frequency offset estimator that is based on the guard interval (GI) present in OFDM signals. We show by simulation that the frequency offset estimator can accurately estimate the frequency misalignment at the sacrifice of limited estimation range.

This letter proposes a novel approach for mel-cepstral analysis based on the psychoacoustic model of MPEG. A perceptual weighting function is developed by applying cubic spline interpolation on the signal-to-mask ratios (SMRs) which are obtained from the psychoacoustic model. Experiments on speaker identification and speech re-synthesis showed that the proposed method not only improved the speaker recognition performance, but also improved the speech quality of the re-synthesized speech.

This letter proves the finish time predictability of EDZL (Earliest Deadline Zero Laxity) scheduling algorithm for multiprocessor real-time systems, which is a variant of EDF. Based on the results, it also shows that EDZL can successfully schedule any periodic task set if its total utilization is not greater than (m+1)/2, where m is the number of processors.

This paper presents a hardware-efficient folding technique for high-order FIR filtering while considering the tradeoff between the number of processing elements and throughput rate. Given the throughput rate, one can always employ the minimum number of processing elements for saving the implementation cost and figure out a folded architecture. However, applying inefficient folding techniques may result in costly switches and registers. Therefore, our work intends to evaluate the efficiency for folding techniques in terms of the number of registers, and the power dissipation of registers. As shown in the estimation results, while comparing with the published folded architectures under the same throughput rate, the proposed folding technique can turn out less power dissipation and low hardware complexity than the others. The proposed design has been implemented using TSMC 0.18 µm 1P6M technology. As seen in the post-layout simulation, our design can meet the requirement of IS-95 WCDMA pulse shaping FIR filter while the power consumption can be as low as 16.66 mW.

One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In MTCMOS circuit, voltage on virtual ground fluctuates due to a discharge current of a logic cell. This event affects to the cell delay and makes static timing analysis (STA) difficult. In this paper, we propose a delay modeling and static STA methodology targeting at MTCMOS circuits. In the proposed method, we prepare a delay look-up table (LUT) consisting of the input slew, the output load capacitance, the virtual ground length, and a power-switch size. Using this LUT, we compute a circuit delay for each logic cell by applying the linear interpolation. This technique enables to calculate the cell delay considering the delay increase by the voltage fluctuation of virtual ground line. Experimental results show that the proposed methodology enables to estimate the cell delay and the critical path delay within 8% errors compared with SPICE simulation.

This paper represents a cycle-based logic simulation method using an LUT cascade emulator, where an LUT cascade consists of multiple-output LUTs (cells) connected in series. The LUT cascade emulator is an architecture that emulates LUT cascades. It has a control part, a memory for logic, and registers. It connects the memory to registers through a programmable interconnection circuit, and evaluates the given circuit stored in the memory. The LUT cascade emulator runs on an ordinary PC. This paper also compares the method with a Levelized Compiled Code (LCC) simulator and a simulator using a Quasi-Reduced Multi-valued Decision Diagram (QRMDD). Our simulator is 3.5 to 10.6 times faster than the LCC, and 1.1 to 3.9 times faster than the one using a QRMDD. The simulation setup time is 2.0 to 9.8 times shorter than the LCC. The necessary amount of memory is 1/1.8 to 1/5.5 of the one using a QRMDD.

Frequency-domain equalization (FDE) based on the minimum mean square error (MMSE) criterion can replace the conventional rake combining while offering significantly improved bit error rate (BER) performance for the downlink DS-CDMA in a frequency-selective fading channel. However, the presence of residual inter-chip-inference (ICI) after FDE produces orthogonality distortion among the spreading codes and the BER performance degrades as the level of multiplexing increases. In this paper, we propose a joint MMSE frequency-domain equalization (FDE) and ICI cancellation to improve the BER performance of the DS-CDMA downlink. In the proposed scheme, the residual ICI replica in the frequency-domain is generated and subtracted from each frequency component of the received signal after MMSE-FDE. The MMSE weight at each iteration is derived taking into account the residual ICI. The effect of the proposed ICI cancellation scheme is confirmed by computer simulation.

Ball Grid Array packages in which I/O pins are arranged in a grid array pattern realize a number of connections between chips and PCB, but it takes much time in manual routing. So the demand for automation of package routing is increasing. In this paper, we give the necessary and sufficient condition that all nets can be connected by monotonic routes when a net consists of a finger and a ball and fingers are on the two parallel boundaries of the Ball Grid Array package, and propose a monotonic routing method based on this condition. Moreover, we give a necessary condition and a sufficient condition when fingers are on the two orthogonal boundaries, and propose a monotonic routing method based on the necessary condition.

Concurrency is one of the most important issues in system-level design. Interleaving among parallel processes can cause an extremely large number of different behaviors, making design and verification difficult tasks. In this work, we propose a synchronization verification method for system-level designs described in the SpecC language. Instead of modeling the design with timed FSMs and using a model checker for timed automata (such as UPPAAL or KRONOS), we formulate the timing constraints with equalities/inequalities that can be solved by integer linear programming (ILP) tools. Verification is conducted in two steps. First, similar to other software model checkers, we compute the reachability of an error state in the absence of timing constraints. Then, if a path to an error state exists, its feasibility is checked by using the ILP solver to evaluate the timing constraints along the path. This approach can drastically increase the sizes of the designs that can be verified. Abstraction and abstraction refinement techniques based on the Counterexample-Guided Abstraction Refinement (CEGAR) paradigm are applied.

We derived explicit formulas for evaluating the error vector magnitude (EVM) from the amplitude distortion (AM-AM) and phase distortion (AM-PM) of power amplifiers (PAs) in orthogonal frequency-division multiplexing (OFDM) systems, such as the IEEE 802.11a/g wireless local area networks (WLANs) standards. We demonstrated that the developed formulas allowed EVM simulation of a memoryless PA using only a single-tone response (i.e. without OFDM modulation and demodulation), thus enabling us to easily simulate the EVM using a harmonic-balance (HB) simulator. This HB simulation technique reduced the processing time required to simulate the EVM of a PA for the IEEE 802.11a standard by a factor of ten compared to a system-level (SL) simulation. We also demonstrated that the measured EVM of a PA module for the IEEE 802.11g could accurately be predicted by applying the measured static AM-AM and AM-PM characteristics to the derived formulas.

In real-time multimedia processing systems a very large part of the power consumption is due to the data storage and data transfer. Moreover, the area cost is often largely dominated by the memory modules. In deriving an optimized (for area and/or power) memory architecture, memory size computation is an important step in the exploration of the possible algorithmic specifications of multimedia applications. This paper presents a novel non-scalar approach for computing exactly the memory size in real-time multimedia algorithms. This methodology uses both algebraic techniques specific to the data-flow analysis used in modern compilers and, also, more recent advances in the theory of polyhedra. In contrast with all the previous works which are only estimation methods, this approach performs exact memory computations even for applications significantly large in terms of the code size, number of scalars, and number of array references.

Software defined radio, which uses reconfigurable signal processing devices, requires the determination of multiple unknown parameters to realize the potential capabilities of adaptive communication. Evolutional algorithms are optimal multi dimensional search techniques, and are well known to be effective for parameter determination. This letter proposes an evolutional algorithm for learning the mobile time-varying channel parameters without any specific assumption of scattering distribution. The proposed method is very simple to realize, but can provide precise channel estimation results. Simulations of an OFDM system show that for an example of OFDM communication under the time-varying fading channel, the proposed learning method can achieve the better BER performance.

Recently, a word-valued source has been proposed as a new class of information source models. A word-valued source is regarded as a source with a probability distribution over a word set. Although a word-valued source is a nonstationary source in general, it has been proved that an entropy rate of the source exists and the Asymptotic Equipartition Property (AEP) holds when the word set of the source is prefix-free. However, when the word set is not prefix-free (non-prefix-free), only an upper bound on the entropy density rate for an i.i.d. word-valued source has been derived so far. In this paper, we newly derive a lower bound on the entropy density rate for an i.i.d. word-valued source with a finite non-prefix-free word set. Then some numerical examples are given in order to investigate the behavior of the bounds.

In this study we have employed an effective technique for dosimetric analyses of base station antennas in an underground environment. The technique combines a ray-tracing method and the finite-difference time-domain (FDTD) method to calculate the specific absorption rate (SAR) in the human body. The ray-tracing method was applied to evaluate the incident fields in relation to the exposed subject in a three-dimensional space, while the FDTD method was used to calculate the detailed SAR distributions in the human body. A scenario under an underground passage with the installation of a top-loaded monopole antenna was analyzed to investigate the relationship between the actual antenna exposure and a plane-wave exposure. The results show that the plane-wave exposure overestimated the whole-body average SAR in most cases, although this was not always true for peak SAR. The finding implies not only the usefulness of the present uniform-exposure-based reference level for the whole-body average SAR evaluation but also the necessity of modeling actual underground environment for high-precision local peak SAR evaluation.

Radio frequency identification (RFID) technology is becoming increasingly attractive because of its high storage capacity and reprogrammability. There is a challenge to be overcome when a reader needs to read a number of tags within the reader's interrogation zone at the same time. In this paper, we present an anti-collision scheme in a RFID system. The scheme is based on the dynamic framed ALOHA protocol developed for radio networks. In our scheme, we propose two methods to estimate the number of tags. Simulation results indicate that the total number of time slots for reading all tags is about 4 times the number of tags that need to be read, including acknowledgement time slots. The main advantages of our scheme are the great performance of uplink throughput and its easy implementation for both readers and tags.