A double surface light emission backlight that uses single light-guide plate, has been developed for illumination of two liquid-crystal displays (LCD) on its front and rear, to be used in a cellular phone. The light-guide plate has a trapezoid cross-section with arrays of optical micro deflector and micro prism on the front and the rear surfaces, respectively. Propagated light, forward and backward, inside the light-guide plate are controlled and directed toward LCDs using only two prism sheets with internal reflection characteristic, each for the front and the rear. Only three optical components and four light-emitting diodes (LEDs) are used in the new structure compared with ten components and six LEDs of the current type. Comparing with the current type, the thickness and power consumption of the new backlight are reduced by a factor of 0.59 and 0.67, respectively.

This letter develops a practical sectorized antenna array using center-fed half-wavelength dipole antennas that are parallel to and a distance in front of a large ground plane reflector. Each element in the array is designed to provide coverage to isolate each 120sector from adjacent sectors. We derive a closed-form expression for spatial correlation function that can be used as guides in evaluating the effects of array spatial correlation on diversity performance in sectorized cellular communications.

In this paper, we propose an optimal bit rate control algorithm which is fully compatible with MPEG-4 or H.263+. The proposed algorithm is designed to identify the optimal quantizer set through Lagrangian optimization when used for optimal bit allocation. To find the optimal quantizer set, we make use of the Viterbi algorithm in order to solve the dependency between quantization parameters of each macroblock due to the unique characteristics of MPEG-4 or H.263+. We set the Lagrangian cost function as a cost function of the Viterbi algorithm. We implement the proposed algorithm in MPEG-4 coders and compare its performance to the VM8 and optimal bit rate control algorithm, using independent quantization parameters in the circumstance of a low bit rate.

This paper describes a new fast learning algorithm for Self-Organizing Map employing a "rough comparison winner-take-all" and its digital hardware architecture. In rough comparison winner-take-all algorithm, the winner unit is roughly and strictly assigned in early and later learning stage, respectively. It realizes both of high accuracy and fast learning. The digital hardware of the self-organizing map with proposed WTA algorithm is implemented using FPGA. Experimental results show that the designed hardware is superior to other hardware with respect to calculation speed.

This paper provides a computational method to construct a Lyapunov function to prove a stability of hybrid automata that can have nonlinear vector fields. Algebraic inequalities and equations are formulated, which are solved via LMI optimization. Numerical examples are presented to illustrate the proposed method.

This paper provides a list-scheduling method for program nets executed with two processors. The program nets dealt with in this paper are acyclic and SWITCH-less, and the priority list proposed in this paper consists of both dynamic and static lists. First, we point out the weakness of a previously proposed priority list and propose a new priority list. Then we give properties of the new priority list and further prove this new priority list can generate optimal schedules for the program nets whose AND-nodes possess at most single input edge. Finally, we compare the new priority list with the previous one to show the new priority list can generate shorter schedules than the previous for the nets whose AND-nodes may have two input edges.

Through many researches on modeling and analyzing biological pathways, Petri net has recognized as a promising method for representing biological pathways. Recently, Matsuno et al. (2003) introduced hybrid functional Petri net (HFPN) for giving more intuitive and natural biological pathway modeling method than existing Petri nets. They also developed Genomic Object Net (GON) which employs the HFPN as a basic architecture. Many kinds of biological pathways have been modeled with the HFPN and simulated by the GON. This paper gives a new HFPN model of "cell cycle of fission yeast" with giving six basic HFPN components of typical biological reactions, and demonstrating the method how biological pathways can be modeled with these HFPN components. Simulation results by GON suggest a new hypothesis which will help biologist for performing further experiments.

To fulfill the computing demands in visual media processing, we have been investigating a parallel processing system to improve the processing speed of the visual media related to applications from the point of view of a memory system within a single instruction multiple data (SIMD) computer. In this paper, we have introduced MAMS-PP4, which is similar to a pipelined SIMD architecture type and consists of pq processing elements (PEs) as well as a multi-access memory system (MAMS). MAMS supports simultaneous access to pq data elements within a horizontal (1 pq), a vertical (pq 1) or a block (p q) subarray with a constant interval in an arbitrary position in an M N array of data elements, where the number of memory modules, m, is a prime number greater than pq. MAMS reduces the memory access time for an SIMD computer and also improves the cost and complexity that involved in controlling the large volume of data demanded in visual media applications. PE is designed to be a two-state machine in order to utilize MAMS efficiently. MAMS-PP4 was fabricated into ASIC using TOSHIBA TC240C series library and a test board was used to measure the performance of ASIC. The test board consists of devices such as an MPC860 embedded-PCI board, two ASICs and a FPGA for the control units. Experiment was done on various computer systems in order to compare the performance of MAMS-PP4 using morphological operations as the application. MAMS-PP4 shows a respectful and consistent processing speed.

Direct digital frequency synthesizers (DDFS) provide fast frequency switching with high spectral purity and are widely used in modern spread spectrum wireless communication systems. ROM-based DDFS uses a ROM lookup table to store the amplitude of a sine wave. A large ROM table is required for high spectral purity. However, a larger ROM uses more area and consumes more power. Several ROM compression methods, including Sunderland technique based on simple trigonometric identities and quantization & error compensation techniques, have been reported. In this paper, we suggest several new techniques to reduce the ROM size. One new technique uses more number of hierarchical levels in ROM structures. Another technique uses simple interpolation techniques combined with hierarchical ROM structures. Experimental results show that the new proposed techniques can reduce the required ROM size up to 24%, when compared to that of a resent approach.

The Hidden Markov Model (HMM) is a popular statistical framework for modeling and analyzing stochastic signals. In this paper, a novel strategy is proposed that makes use of level-building algorithm with a chain of AdaBoost HMM classifiers to model long stochastic processes. AdaBoost HMM classifier belongs to the class of multiple-HMM classifier. It is specially trained to identify samples with erratic distributions. By connecting the AdaBoost HMM classifiers, processes of arbitrary length can be modeled. A probability trellis is created to store the accumulated probabilities, starting frames and indices of each reference model. By backtracking the trellis, a sequence of best-matched AdaBoost HMM classifiers can be decoded. The proposed method is applied to visual speech processing. A selected number of words and phrases are decomposed into sequences of visual speech units using both the proposed strategy and the conventional level-building on HMM method. Experimental results show that the proposed strategy is able to more accurately decompose words/phrases in visual speech than the conventional approach.

Reconfigurable logic circuitry has special importance because the popularity of Field Programmable Gate Arrays (FPGA) based applications. A reconfigurable logic based on FGMOS transistors, where a single stage can perform binary operations as well as state machines, is presented. The use of the proposed logic allows the integration of several stages into a single chip because their small area requirement, low voltage and low power characteristics.

This paper presents circuit techniques using pulse-width and pulse-phase modulation (PWM/PPM) approaches for VLSI implementation of nonlinear dynamical systems. The proposed circuits implement discrete-time continuous-state dynamics by means of analog processing in a time domain, and also approximately implement continuous-time dynamics. Arbitrary nonlinear transformation functions are generated by the process in which a PPM signal samples a voltage or current source whose waveform in the time domain has the same shape as the desired transformation function. Because a shared arbitrary nonlinear voltage or current waveform generator can be constructed by digital circuits and D/A converters, high flexibility and real-time controllability are achieved. By using one of these new techniques, we have designed and fabricated a CMOS chaos circuit with arbitrary 1-D maps using a 0.6 µm CMOS process, and demonstrate from the experimental results that the new chaos circuit successfully generated various chaos with 7.5-7.8 bit precision by using logistic, tent and chaotic-neuron maps.

A batch process is a typical concurrent system in which multiple interacting tasks are carried out in parallel on several batches at the same time. A major difficulty in designing a batch control system is the lack of modeling techniques. This paper aims at developing a method of constructing batch control system models in a hierarchical manner and operating batch processes using the constructed models. For this purpose, it first defines process and plant specifications described by partial languages, next presents a procedure for constructing hierarchical Petri net based models, and states the verification of models based on reachability analysis. It also discusses the detection of faults and conflicts in batch processes based on place-invariant analysis.

Many simulated annealing algorithms use the Cauchy neighbors for fast convergence, and the conventional method uses the product of n one-dimensional Cauchy distributions as an approximation. However, this method slows down the search severely as the dimension gets high because of the dimension-wise neighbor generation. In this paper, we analyze the orthogonal neighbor characteristics of the conventional method and propose a method of generating symmetric neighbors from the n-dimensional Cauchy distribution. The simulation results show that the proposed method is very effective for the search in the simulated annealing and can be applied to many other stochastic optimization algorithms.

The maximum a posteriori (MAP) algorithm is the optimum solution for decoding concatenated codes, such as turbo codes. Since the MAP algorithm is computationally complex, more efficient algorithms, such as the Max-Log-MAP algorithm and the soft-output Viterbi algorithm (SOVA), can be used as suboptimum solutions. Especially, the Max-Log-MAP algorithm is widely used, due to its near-optimum performance and lower complexity compared with the MAP algorithm. In this paper, we propose an efficient algorithm for decoding concatenated codes by modifying the Max-Log-MAP algorithm. The efficient implementation of the backward recursion and the log-likelihood ratio (LLR) update in the proposed algorithm improves its computational efficiency. Memory is utilized more efficiently if the sliding window algorithm is adopted. Computer simulations and analysis show that the proposed algorithm requires a considerably lower number of computations compared with the Max-Log-MAP algorithm, while providing the same overall performance.

This paper addresses the scheduling problem of a class of automated manufacturing systems with multiple resource requests. In the automated manufacturing system model, a set of jobs is to be processed and each job requires a sequence of operations. Each operation may need more than one resource type and multiple identical units with the same resource type. Upon the completion of an operation, resources needed in the next operation of the same job cannot be released and the remaining resources cannot be released until the start of the next operation. The scheduling problem is formulated by Timed Petri nets model under which the scheduling goal consists in sequencing the transition firing sequence in order to avoid the deadlock situation and to minimize the makespan. In the proposed genetic algorithm with deadlock-free constraint, Petri net transition sequence is coded and a deadlock detection method based on D-siphon technology is proposed to reschedule the sequence of transitions. The enabled transitions should be fired as early as possible and thus the quality of solutions can be improved. In the fitness computation procedure, a penalty item for the infeasible solution is involved to prevent the search process from converging to the infeasible solution. The method proposed in this paper can get a feasible scheduling strategy as well as enable the system to achieve good performance. Numerical results presented in the paper show the efficiency of the proposed algorithm.

The MPEG-2 Test Model 5 (TM5) algorithm describes a rate control method which consists of three steps: bit allocation, rate control and modulation. In TM5, however, buffer overflow and picture quality degradation may occur at the end of the GOP because the target bits and the actual coding bits for each picture do not match well. This paper presents a new bit rate control algorithm for matching the target and the actual coding bits based on accurate bit allocation. The key idea of the proposed algorithm is to determine quantization parameters which enable us to generate the actual coding bits close to the target bits for each picture, while improving the picture quality. The proposed algorithm exploits the relationship between the number of the actual coding bits and the number of the estimated bits of the previous macroblock within a picture.

Voice over Internet protocol (VoIP) is to transfer voice packets over IP networks, while voice signal is processed by using digital signal processing technology before being transmitted. VoIP quality cannot be expected, because it is hard to predict the influence of delay, packet loss rate, packet error, etc. It is difficult to rebuild the voice wave form, if a large amount of voice packets are lost. This paper mainly studies on how to maintain a better voice quality over hybrid fiber/coaxial (HFC) networks, if it is inevitable to drop packets. We particularly consider the data over cable service interface specification (DOCSIS) version 1.1 with the unsolicited grant service with activity detection (UGS/AD) for VoIP services. We propose a smallest successive times first (SSTF) scheduling algorithm to schedule VoIP packets for cable modem termination system (CMTS), which can support fair transmission and long-term transmission continuity for VoIP connections. We analyze voice quality about continuity of the transmitted VoIP packets, consecutive clipping times, and VoIP packet drop rate for all connections. Performance measurement shows excellent results for the proposed algorithm by simulation experiments and objective evaluation.

In this paper, we consider a blind channel estimation and equalization for single input multiple output (SIMO) channels. It is based on the one-step forward multichannel linear prediction error method. The derivation of the existing method is based on the noiseless assumption, however, we analyze the effects of additive noise at the output of the one-step forward multichannel linear prediction error filters. Moreover, we derive analytical results for the error in the blind channel estimation and equalization using linear prediction.

Fairness is one of the most important features of a rate allocation strategy. Proportional fairness criterion has been recently proposed by F. P. Kelly and his colleagues. In this paper, we have proposed a two-level hierarchical technique which allocates proportionally-fair rates to the network elastic users. Part of the network links which are used commonly by the end-users and are congestion prone, constitute the higher (first) level of the hierarchy. In this level, the users with common path in the network are grouped as virtual users. End-users and remaining network links constitute the lower (second) level of hierarchy. To improve the convergence rate of the algorithm, a combination of Jacobi method and fuzzy techniques is deployed in the higher level of hierarchy. Implementing such fast algorithms in the higher level (which is topologically simpler than the whole network), reduces the computational complexity with respect to the use of such algorithms in the whole network. Additionally, the lower level penalty function computation is done once in each N iterations, which reduces the computational complexity furthermore. The simulation results show that the proposed algorithm outperforms that of Kelly in the convergence speed.