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12841-12860hit(20498hit)

  • A Fully Integrated Current-Steering 10-b CMOS D/A Converter with On-Chip Terminated Resistors

    Sanghoon HWANG  Minkyu SONG  

     
    PAPER-Integrated Electronics

      Vol:
    E87-C No:12
      Page(s):
    2179-2185

    A fully integrated current-steering 10-b CMOS Digital-to-Analog Converter with on-chip terminated resistors is presented. In order to improve the device-mismatching problem of internal termination resistors, a self-calibrated current bias circuit is designed. With the self-calibrated current bias circuit, the gain error of the output voltage swing is reduced within 0.5%. For the purpose of reducing glitch noises, furthermore, a novel current switch based on a deglitching circuit is proposed. The prototype circuit has been fabricated with a 3 V 0.35 µm 2-poly 3-metal CMOS technology, and it occupies 1350 µm750 µm silicon area with 45 mW power consumption. The measured INL and DNL are within 0.5LSB, respectively. The measured SFDR is about 65 dB, when an input signal is about 8 MHz at 100 MHz clock frequency.

  • Design and Implementation of Lifeline Communication System in the Internet

    Takahiro KIKUCHI  Masaaki NORO  Katsuyuki YAMAZAKI  Hideki SUNAHARA  Shinji SHIMOJO  

     
    PAPER-Internet Systems

      Vol:
    E87-D No:12
      Page(s):
    2714-2722

    As Internet access had spread, it has become an important potential means of lifeline communication. The Internet can fulfill a role in the everyday life of citizens by offering lifeline communication services such as the police, ambulance, gas, electricity, and water services when an emergency occurs. In these lifeline communications, a caller needs to be able to communicate with the nearby lifeline service in the same manner as on a PSTN (Public Switched Telephone Networks) without being consciously aware of the path the caller's message is taking. Moreover, the lifeline service agency must be able to acquire the caller's location and identity. However, it is very difficult to transfer these essential functions from the PSTN to the Internet without making significant changes, because of large differences between the PSTN and the Internet. In this paper, we discuss how to obtain these functions for lifeline communications in the Internet. We further propose a model and implement a lifeline communication system on the Internet.

  • Performance Analysis of MRC 2D-RAKE Receivers in Correlated Nakagami-m Fading

    Kaizhi HUANG  Jing WANG  

     
    PAPER-Wireless Communication Technologies

      Vol:
    E87-B No:12
      Page(s):
    3663-3672

    In this paper, the bit error rate (BER) and the outage probability are presented for a maximal ratio combining (MRC) two-dimensional (2D)-RAKE receiver operating in a correlated frequency-selective Nakagami-m fading environment with multiple access interference. A simple approximated probability distribution function of the signal-to-interference-plus-noise ratio (SINR) is derived for the receiver with multiple correlated antennas and RAKE branches in arbitrary fading environments. The combined effects of spatial and temporal diversity order, average received signal-to-noise ratio, the number of multiple access interference, angular spread, antennae spacing and multi-path Nakagami-m fading environment on the system performance are illustrated. Numerical results indicate that the performance of the 2D-RAKE receiver depends highly on the operating environment and antenna array configuration. The performance can be improved by increasing the spatio-temporal diversity gains and antenna spacing.

  • Analysis of Resonant Frequency of Fast Scanning Micromirror with Vertical Combdrives

    Hiroyuki WADA  Daesung LEE  Stefan ZAPPE  Olav SOLGAARD  

     
    LETTER-Electromechanical Devices and Components

      Vol:
    E87-C No:11
      Page(s):
    2006-2008

    The relation between resonant frequency of micromirror with vertical combdrives and applied voltage between the upper and lower comb teeth was analyzed. Resonant frequency of the micromirror was controlled by stiffness of the torsion hinge. Resonant frequency of the mirror was proportional to the applied voltage between the upper and lower comb teeth at the same tilt angle.

  • Pretilt Angle of Liquid Crystals Induced by Photo-Aligned Films of Polyimide Containing Azobenzene in the Backbone Structure

    Kenji SAKAMOTO  Kiyoaki USAMI  Toru SASAKI  Sukekatsu USHIODA  

     
    INVITED PAPER

      Vol:
    E87-C No:11
      Page(s):
    1936-1942

    We have investigated the pretilt angle of liquid crystal (LC) molecules induced by photo-alignment films of polyimide (Azo-PI) containing azobenzene in the backbone structure. To generate finite pretilt angles, the Azo-PI film with inclined alignment of the backbone structure was prepared by a double light-exposure method. In this method the corresponding polyamic acid (Azo-PAA) film was first exposed to linearly polarized ultraviolet/visible (UV/VIS) light (LP-light) at normal incidence, and then oblique angle irradiation of unpolarized UV/VIS light (UP-light) was performed in the plane of incidence perpendicular to the polarization direction of the LP-light. Repeated photo-isomerization reactions of azobenzene induce the alignment of the Azo-PAA backbone structure. By thermally imidizing the photo-treated film we obtained a thermally and optically stable Azo-PI film. The orientational distribution of the Azo-PI backbone structure was determined by measuring the polarized infrared absorption spectra as a function of the sample rotation angle and the angle of incidence. The pretilt angle of LC molecules was determined by a crystal rotation method. We found that the average inclination angle of the Azo-PI backbone structure increased with the UP-light exposure. The pretilt angle of LC molecules, measured from the surface plane, also increased with the UP-light exposure. We succeeded in generating a pretilt angle of 3. The relation between the LC pretilt angle and the average inclination angle of the Azo-PI backbone structure is discussed.

  • New Cell Configuration for High Resolution PDPs with Stripe Rib and Discharge Deactivation Film

    Shinichiro NAGANO  Keisuke JO  Katsuhiro HIROSE  Hideji KAWARAZAKI  

     
    INVITED PAPER

      Vol:
    E87-C No:11
      Page(s):
    1962-1969

    We propose a new cell configuration which newly employs discharge deactivation film (DDF). DDF is formed on MgO surface in stripe figure to cover it around the boundary of neighboring display lines. DDF prevents discharge cross talk between the lines even in case of stripe rib structure by virtue of its low secondary electron emission coefficient (γi). DDF also makes better address discharge response because it presumably moves address discharge closer to the surface dischage gap. On behalf of mass productivity for large size PDPs DDF is formed by simple screen-printing and firing method. And it consists of very fine Al2O3 grains without any inorganic binder. Such DDF is visually transparent and then helpful for high luminance and luminous efficiency. In addition to it, such DDF is presumably equipped with gas purifying character and then helpful for deep blue color and good white color balance accordingly. Further, DDF combined with sustain electrodes in specific figure which we call "CAPABLE DDF" brings about so high luminous efficiency for stripe rib structure as it may surpass box rib one. This probably means that vertically open discharge space in stripe rib structure is advantageous for high luminous efficiency. In our latest work for 46 inch-high definition PDPs, 2.1 lm/W and 1200 cd/m2 were both achieved under practical driving condition. Still it will be as high as 2.4 lm/W if each sustain electrode is shared by neighboring display lines. CAPABLE DDF allows more tolerance in DDF printing process. It also makes optical cross talk negligible even in stripe rib structure. And its durability against long time operation proved to have no specific problem. This presumably means that re-landing of sputtered MgO never reaches DDF surface. We believe this new technology can promise the future of stripe rib.

  • Efficient Masquerade Detection Using SVM Based on Common Command Frequency in Sliding Windows

    Han-Sung KIM  Sung-Deok CHA  

     
    PAPER-Application Information Security

      Vol:
    E87-D No:11
      Page(s):
    2446-2452

    Masqueraders who impersonate other users pose serious threat to computer security. Unfortunately, firewalls or misuse-based intrusion detection systems are generally ineffective in detecting masqueraders. Anomaly detection techniques have been proposed as a complementary approach to overcome such limitations. However, they are not accurate enough in detection, and the rate of false alarm is too high for the technique to be applied in practice. For example, recent empirical studies on masquerade detection using UNIX commands found the accuracy to be below 70%. In this research, we performed a comparative study to investigate the effectiveness of SVM (Support Vector Machine) technique using the same data set and configuration reported in the previous experiments. In order to improve accuracy of masquerade detection, we used command frequencies in sliding windows as feature sets. In addition, we chose to ignore commands commonly used by all the users and introduce the concept of voting engine. Though still imperfect, we were able to improve the accuracy of masquerade detection to 80.1% and 94.8%, whereas previous studies reported accuracy of 69.3% and 62.8% in the same configurations. This study convincingly demonstrates that SVM is useful as an anomaly detection technique and that there are several advantages SVM offers as a tool to detect masqueraders.

  • Control of Batch Processes Based on Hierarchical Petri Nets

    Tomoyuki YAJIMA  Takashi ITO  Susumu HASHIZUME  Hidekazu KURIMOTO  Katsuaki ONOGI  

     
    PAPER-Concurrent Systems

      Vol:
    E87-A No:11
      Page(s):
    2895-2904

    A batch process is a typical concurrent system in which multiple interacting tasks are carried out in parallel on several batches at the same time. A major difficulty in designing a batch control system is the lack of modeling techniques. This paper aims at developing a method of constructing batch control system models in a hierarchical manner and operating batch processes using the constructed models. For this purpose, it first defines process and plant specifications described by partial languages, next presents a procedure for constructing hierarchical Petri net based models, and states the verification of models based on reachability analysis. It also discusses the detection of faults and conflicts in batch processes based on place-invariant analysis.

  • Optimized Power Control Using LQ Scheme for CDMA Systems

    Ji-Young BYUN  Young-Chai KO  Kwan-Ho YOU  

     
    LETTER

      Vol:
    E87-A No:11
      Page(s):
    2909-2912

    In this paper, we propose an optimal power control algorithm with fast convergence rate for CDMA cellular systems. The new power control algorithm is based on linear quadratic control theory (LQR). Using the state feedback control designed to minimize an objective function, each mobile performs a successful transmission with optimal power. Simulation results show a fast convergence rate to target SIR with less power consumption, and an augmented channel capacity through decreased outage probability.

  • Fast Learning Algorithms for Self-Organizing Map Employing Rough Comparison WTA and its Digital Hardware Implementation

    Hakaru TAMUKOH  Keiichi HORIO  Takeshi YAMAKAWA  

     
    PAPER

      Vol:
    E87-C No:11
      Page(s):
    1787-1794

    This paper describes a new fast learning algorithm for Self-Organizing Map employing a "rough comparison winner-take-all" and its digital hardware architecture. In rough comparison winner-take-all algorithm, the winner unit is roughly and strictly assigned in early and later learning stage, respectively. It realizes both of high accuracy and fast learning. The digital hardware of the self-organizing map with proposed WTA algorithm is implemented using FPGA. Experimental results show that the designed hardware is superior to other hardware with respect to calculation speed.

  • n-Dimensional Cauchy Neighbor Generation for the Fast Simulated Annealing

    Dongkyung NAM  Jong-Seok LEE  Cheol Hoon PARK  

     
    LETTER-Algorithm Theory

      Vol:
    E87-D No:11
      Page(s):
    2499-2502

    Many simulated annealing algorithms use the Cauchy neighbors for fast convergence, and the conventional method uses the product of n one-dimensional Cauchy distributions as an approximation. However, this method slows down the search severely as the dimension gets high because of the dimension-wise neighbor generation. In this paper, we analyze the orthogonal neighbor characteristics of the conventional method and propose a method of generating symmetric neighbors from the n-dimensional Cauchy distribution. The simulation results show that the proposed method is very effective for the search in the simulated annealing and can be applied to many other stochastic optimization algorithms.

  • Computing with Waves in Chemical Media: Massively Parallel Reaction-Diffusion Processors

    Andrew ADAMATZKY  

     
    INVITED PAPER

      Vol:
    E87-C No:11
      Page(s):
    1748-1756

    A reaction-diffusion computer is a large-scale array of elementary processors, micro-volumes of chemical medium, which act, change their states determined by chemical reactions, concurrently and interact locally, via local diffusion of chemical species; it transforms data to results, both represented by concentration profiles of chemical species, by traveling and colliding waves in spatially extended chemical media. We show that reaction-diffusion processors, simulated or experimental, can solve a variety of tasks, including computational geometry, robot navigation, logics and arithmetics.

  • Hybrid Dynamic-Grouping Bandwidth Reservation Scheme for Multimedia Wireless Networks

    Jau-Yang CHANG  Hsing-Lung CHEN  

     
    PAPER-Wireless Communication Technologies

      Vol:
    E87-B No:11
      Page(s):
    3264-3273

    Next generation wireless networks are expected to support multimedia applications (audio phone, video on demand, video conference, file transfer, etc.). Multimedia applications make a great demand for bandwidth and impose stringent quality of service (QoS) requirements on the wireless networks. In order to provide mobile hosts with high QoS, efficient and better bandwidth reservation is necessary in multimedia wireless networks. This paper presents a novel hybrid dynamic-grouping bandwidth reservation scheme to support QoS guarantees in the next generation wireless networks. The proposed scheme is based on probabilistic resource estimation to provide QoS guarantees for multimedia traffic in cellular networks. We establish several reservation time-sections, called groups, according to the mobility information of mobile hosts (MHs) of each base station (BS). The amount of reserved bandwidth for each BS is dynamically adjusted for each reservation group. We use the hybrid dynamic-grouping bandwidth reservation scheme to decrease the connection-dropping probability (CDP) and connection-blocking probability (CBP), while increasing the bandwidth utilization. The simulation results show that the hybrid dynamic-grouping bandwidth reservation scheme provides less CDP and less CBP, and achieves high bandwidth utilization.

  • A Single-Electron-Transistor Logic Gate Family for Binary, Multiple-Valued and Mixed-Mode Logic

    Katsuhiko DEGAWA  Takafumi AOKI  Tatsuo HIGUCHI  Hiroshi INOKAWA  Yasuo TAKAHASHI  

     
    PAPER

      Vol:
    E87-C No:11
      Page(s):
    1827-1836

    This paper presents a model-based study of SET (Single-Electron-Transistor) logic gate family for synthesizing binary, MV (Multiple-Valued) and mixed-mode logic circuits. The use of SETs combined with MOS transistors allows compact realization of basic logic functions that exhibit periodic transfer characteristics. The operation of basic SET logic gates is successfully confirmed through SPICE circuit simulation based on the physical device model of SETs. The proposed SET logic gates are useful for implementing binary logic circuits, MV logic circuits and binary-MV mixed-mode logic circuits in a highly flexible manner. As an example, this paper describes design of various parallel counters for carry-propagation-free arithmetic, where MV signals are effectively used to achieve higher functionality with lower hardware complexity.

  • Deadlock-Free Scheduling in Automated Manufacturing Systems with Multiple Resource Requests

    Zhonghua HUANG  Zhiming WU  

     
    PAPER-Concurrent Systems

      Vol:
    E87-A No:11
      Page(s):
    2844-2851

    This paper addresses the scheduling problem of a class of automated manufacturing systems with multiple resource requests. In the automated manufacturing system model, a set of jobs is to be processed and each job requires a sequence of operations. Each operation may need more than one resource type and multiple identical units with the same resource type. Upon the completion of an operation, resources needed in the next operation of the same job cannot be released and the remaining resources cannot be released until the start of the next operation. The scheduling problem is formulated by Timed Petri nets model under which the scheduling goal consists in sequencing the transition firing sequence in order to avoid the deadlock situation and to minimize the makespan. In the proposed genetic algorithm with deadlock-free constraint, Petri net transition sequence is coded and a deadlock detection method based on D-siphon technology is proposed to reschedule the sequence of transitions. The enabled transitions should be fired as early as possible and thus the quality of solutions can be improved. In the fitness computation procedure, a penalty item for the infeasible solution is involved to prevent the search process from converging to the infeasible solution. The method proposed in this paper can get a feasible scheduling strategy as well as enable the system to achieve good performance. Numerical results presented in the paper show the efficiency of the proposed algorithm.

  • Experimental Determination of Propagation Paths for the ETC System--Equipment Development and Field Test--

    Katsuyuki HANEDA  Jun-ichi TAKADA  Takeo IWATA  Yoshitaka WAKINAKA  Takeshi KUNISHIMA  

     
    PAPER-Intelligent Transport System

      Vol:
    E87-A No:11
      Page(s):
    3008-3015

    Electronic Toll Collection (ETC), an application of Dedicated Short Range Wireless Communication (DSRC), had suffered from wrong operations due to multipath problems. To solve this problem, we proposed to apply a simple configured path determination scheme for the ETC system. The system consists of a vector network analyzer, low-noise amplifier, and X-Y positioner and achieves an automatic measurement of the spatial transfer function with emphasis on accurate measurement and reproducibility. For the reliable identification of the propagating paths, 3-D Unitary ESPRIT and SAGE algorithms were employed. Having developed the system, field experiments at the toll gate of the highway was carried out. In the measurements, we could determine many propagation paths so that the dominant propagation phenomena at the toll gate was identified. They included a ground-canopy twice reflected wave, which was a potential path that caused wrong operation. Consequently, their reflection coefficients and polarization characteristics were investigated. From the results, applicability of the path determination system for short range on-site measurement was confirmed.

  • On Optimization in Composition of Concurrent Formal Specifications

    Bhed Bahadur BISTA  

     
    LETTER

      Vol:
    E87-A No:11
      Page(s):
    2905-2908

    LOTOS parallel operator, which is a binary operator, is used to combine processes in order to express their concurrency. Unlike other LOTOS operators, various possibilities exist when combining processes by the parallel operator. If two processes are selected randomly for combining, the size of the composite intermediate process after combining may be large. In this paper, we propose an algorithm for selecting two processes out of three or more processes so that the size of the intermediate process is the smallest when combined by the parallel operator. Smaller size of an intermediate process means it takes less memory space which is very important in designing verification tools for systems or communication protocols specified in LOTOS.

  • New Effective ROM Compression Methods for ROM-Based Direct Digital Frequency Synthesizer Design

    Jinchoul LEE  Hyunchul SHIN  

     
    LETTER-Devices/Circuits for Communications

      Vol:
    E87-B No:11
      Page(s):
    3352-3355

    Direct digital frequency synthesizers (DDFS) provide fast frequency switching with high spectral purity and are widely used in modern spread spectrum wireless communication systems. ROM-based DDFS uses a ROM lookup table to store the amplitude of a sine wave. A large ROM table is required for high spectral purity. However, a larger ROM uses more area and consumes more power. Several ROM compression methods, including Sunderland technique based on simple trigonometric identities and quantization & error compensation techniques, have been reported. In this paper, we suggest several new techniques to reduce the ROM size. One new technique uses more number of hierarchical levels in ROM structures. Another technique uses simple interpolation techniques combined with hierarchical ROM structures. Experimental results show that the new proposed techniques can reduce the required ROM size up to 24%, when compared to that of a resent approach.

  • Modeling and Simulation of Fission Yeast Cell Cycle on Hybrid Functional Petri Net

    Sachie FUJITA  Mika MATSUI  Hiroshi MATSUNO  Satoru MIYANO  

     
    PAPER-Hybrid Systems

      Vol:
    E87-A No:11
      Page(s):
    2919-2928

    Through many researches on modeling and analyzing biological pathways, Petri net has recognized as a promising method for representing biological pathways. Recently, Matsuno et al. (2003) introduced hybrid functional Petri net (HFPN) for giving more intuitive and natural biological pathway modeling method than existing Petri nets. They also developed Genomic Object Net (GON) which employs the HFPN as a basic architecture. Many kinds of biological pathways have been modeled with the HFPN and simulated by the GON. This paper gives a new HFPN model of "cell cycle of fission yeast" with giving six basic HFPN components of typical biological reactions, and demonstrating the method how biological pathways can be modeled with these HFPN components. Simulation results by GON suggest a new hypothesis which will help biologist for performing further experiments.

  • Self-Organizing Neural Networks by Construction and Pruning

    Jong-Seok LEE  Hajoon LEE  Jae-Young KIM  Dongkyung NAM  Cheol Hoon PARK  

     
    PAPER-Biocybernetics, Neurocomputing

      Vol:
    E87-D No:11
      Page(s):
    2489-2498

    Feedforward neural networks have been successfully developed and applied in many areas because of their universal approximation capability. However, there still remains the problem of determining a suitable network structure for the given task. In this paper, we propose a novel self-organizing neural network which automatically adjusts its structure according to the task. Utilizing both the constructive and the pruning procedures, the proposed algorithm finds a near-optimal network which is compact and shows good generalization performance. One of its important features is reliability, which means the randomness of neural networks is effectively reduced. The resultant networks can have suitable numbers of hidden neurons and hidden layers according to the complexity of the given task. The simulation results for the well-known function regression problems show that our method successfully organizes near-optimal networks.

12841-12860hit(20498hit)