A novel Multiple-Valued Field-Programmable VLSI (MV-FPVLSI) architecture using the Multiple-Valued Source-Coupled Logic (MVSCL) is proposed to implement special-purpose processors. An MV-FPVLSI consists of identical cells, which are connected to 8-neighborhood ones. To reduce the complexity of the interconnection block between two cells in an MV-FPVLSI, a bit-serial fine-grain pipeline architecture is introduced which allows single-wire data transmission and as a result, the data-transmission delay becomes very small in comparison with that of a conventional FPGA. To reduce the number of switches in the interconnection block further, a cell, using multiple-valued source-coupled logic circuits, is proposed, where the input currents can be linearly summed just by wiring without using any active devices. Not only the data, but also the control signal can be superposed by linear summation. As a result, no input switch is required which contributes to smaller data transmission delay. Moreover, an arbitrary 2-input logic function can be generated by linear summation of the input currents and threshold operations using these reconfigurable MVSCL circuits. As the MVSCL circuit has high driving capability in comparison with that of an equivalent CMOS circuit, high-speed logic operation is also possible while maintaining low power.

This paper proposes a simple method for estimation and compensation of signal direction, to deal with relative change of sound source location caused by the movements of a microphone array and a sound source. This method introduces a delay filter that has shifted and sampled sinc functions. This paper presents a concept for the joint optimization of arrival time differences and of the coordinate system of a mobile microphone array. We use the LMS algorithm to derive this method by maintaining a certain relationship between the directions of the microphone array and the sound source directions. This method directly estimates the relative directions of the microphone array to the sound source directions by minimizing the relative differences of arrival time among the observed signals, not by estimating the time difference of arrival (TDOA) between two observed signals. This method also compensates the time delay of the observed signals simultaneously, and it has a feature to maintain that the output signals are in phase. Simulation results support effectiveness of the method.

This paper introduces a methodology for simulating single-electron-transistor (SET)-based multiple-valued logics (MVLs). First, a physics-based analytical model for SET is described, and then a procedure for extracting parameters from measured characteristics is explained. After that, simulated and experimental results for basic MVL circuits are compared. As an advanced example of SET-based logics, a latched parallel counter, which is one of the most important components in arithmetic circuits, is newly designed and analyzed by a simulation. It is found that a SET-based 7-3 counter can be constructed with less than 1/10 the number of devices needed for a conventional circuit and can operate at a moderate speed with 1/100 the conventional power consumption.

Some conventional beamformers require the direction of the desired signal. The performance of such beamformers can substantially be degraded even in the presence of small error on the directional information. In this letter, we propose a prefilter-type beamforming scheme robust to directional error by employing a simple compensator. The performance of the proposed scheme is verified by computer simulation.

We propose a new cell configuration which newly employs discharge deactivation film (DDF). DDF is formed on MgO surface in stripe figure to cover it around the boundary of neighboring display lines. DDF prevents discharge cross talk between the lines even in case of stripe rib structure by virtue of its low secondary electron emission coefficient (γi). DDF also makes better address discharge response because it presumably moves address discharge closer to the surface dischage gap. On behalf of mass productivity for large size PDPs DDF is formed by simple screen-printing and firing method. And it consists of very fine Al2O3 grains without any inorganic binder. Such DDF is visually transparent and then helpful for high luminance and luminous efficiency. In addition to it, such DDF is presumably equipped with gas purifying character and then helpful for deep blue color and good white color balance accordingly. Further, DDF combined with sustain electrodes in specific figure which we call "CAPABLE DDF" brings about so high luminous efficiency for stripe rib structure as it may surpass box rib one. This probably means that vertically open discharge space in stripe rib structure is advantageous for high luminous efficiency. In our latest work for 46 inch-high definition PDPs, 2.1 lm/W and 1200 cd/m2 were both achieved under practical driving condition. Still it will be as high as 2.4 lm/W if each sustain electrode is shared by neighboring display lines. CAPABLE DDF allows more tolerance in DDF printing process. It also makes optical cross talk negligible even in stripe rib structure. And its durability against long time operation proved to have no specific problem. This presumably means that re-landing of sputtered MgO never reaches DDF surface. We believe this new technology can promise the future of stripe rib.

This paper presents a novel architecture to solve two problems of existing FPGAs : the large delay and area due to complex programmable switch blocks, and the large area due to coarse-grain logic blocks that are underutilized to a great degree. A mesh-connected cellular array based on a bit-serial pipeline architecture is introduced to minimize complexity of switch blocks. A fine-grain logic block architecture with a functionality of a bit-serial adder is presented to minimize the number of inputs and outputs of the logic block since increase in the number of inputs and outputs directly increases the complexity of a switch block. For an area-efficient design, the logic block is implemented based on a hybrid of a programmable logic gate and a dedicated carry logic. The hybrid architecture allows us to use a small lookup table to implement the logic gate. Moreover, the carry logic uses a functional pass-gate that merges both logic and storage functions compactly. The performance of the fine-grain field-programmable VLSI (FPVLSI) is evaluated to be more than 2 times higher than that of a coarse-grain FPVLSI.

In this paper, a new computing paradigm suitable for analog circuit systems is described in comparison to the digital circuit systems. The analog circuit systems have some disadvantages especially in terms of accuracy and stability, but there are some applications that don't require accuracy or stability in circuit component. The new computing concept for such applications, 'inaccurate' information processing, or 'rough' information processing, is proposed and described as well as some examples of such applications.

This paper presents a multi-resolution optical flow estimation method that is robust against large variation in the estimation parameter. For each level solution of the multi-grid estimation, a nonlinear iteration is proposed differently from the existing method, where the incremental displacement from the coarser level optical flow is calculated by linear iteration. The experimental results show that the proposed scheme has better error-performance in a much wider range of regularization parameters.

A low-power high-frequency sinusoidal quadrature oscillator is presented through a new RC technique using only CMOS current mirrors. The technique is relatively simple based on (1) internal capacitances of CMOS current mirrors and (2) a resistor of a CMOS current mirror for a negative resistance. Neither external capacitances nor inductances are required. As a particular example, a 2.4 GHz-0.4 mW, 0.325-fT, CMOS sinusoidal quadrature oscillator has been demonstrated. The power consumption is very low at approximately 0.4 mW. Total harmonic distortions (THD) are less than 0.3%. The oscillation frequency is current-tunable over a range of 540 MHz or 22%. The amplitude matching and the quadrature phase matching are better than 0.035 dB and 0.15, respectively. A figure of merit called a normalized carrier-to-noise ratio (CNRnorm) is 158.79 dBc/Hz at the 2 MHz offset from 2.46 GHz. Comparisons to other approaches are also presented.

This paper is concerned with improving noise-robustness of a multi-SNR multi-band speaker identification system by introducing automatic adjustment of subband likelihood recombination weights. The adjustment is performed on the basis of subband power calculated from the noise observed just before the speech starts in the input signal. To evaluate the noise-robustness of this system, text-independent speaker identification experiments were conducted on speech data corrupted with noises recorded in five environments: "bus," "car," "office," "lobby," and "restaurant". It was found that the present method reduces the identification error by 15.9% compared with the multi-SNR multi-band method with equal recombination weights at 0 dB SNR. The performance of the present method was compared with a clean fullband method in which a speaker model training is performed on clean speech data, and spectral subtraction is applied to the input signal in the speaker identification stage. When the clean fullband method without spectral subtraction is taken as a baseline, the multi-SNR multi-band method with automatic adjustment of recombination weights attained 56.8% error reduction on average, while the average error reduction rate of the clean fullband method with spectral subtraction was 11.4% at 0 dB SNR.

Nonminimum phase systems are difficult to be controlled with a conventional PID-type controller because of their inherent characteristics of undershooting. A neuro-controller combined with a PID-type controller has been shown to improve the control performance of the nonminimum phase systems while maintaining stability. In this paper, we apply a multiobjective evolutionary optimization method for training the neuro-controller to reduce the undershooting of the nonminimum phase system. The computer simulation shows that the proposed multiobjective approach is very effective and suitable because it can minimize the control error as well as reduce undershooting and chattering. This method can be applied to many industrial nonminimum phase problems with ease.

Feedforward neural networks have been successfully developed and applied in many areas because of their universal approximation capability. However, there still remains the problem of determining a suitable network structure for the given task. In this paper, we propose a novel self-organizing neural network which automatically adjusts its structure according to the task. Utilizing both the constructive and the pruning procedures, the proposed algorithm finds a near-optimal network which is compact and shows good generalization performance. One of its important features is reliability, which means the randomness of neural networks is effectively reduced. The resultant networks can have suitable numbers of hidden neurons and hidden layers according to the complexity of the given task. The simulation results for the well-known function regression problems show that our method successfully organizes near-optimal networks.

Reconfigurable logic circuitry has special importance because the popularity of Field Programmable Gate Arrays (FPGA) based applications. A reconfigurable logic based on FGMOS transistors, where a single stage can perform binary operations as well as state machines, is presented. The use of the proposed logic allows the integration of several stages into a single chip because their small area requirement, low voltage and low power characteristics.

An experimental model of a redox microarray, which provides a foundation for constructing future massively parallel molecular computers, is proposed. The operation of a redox microarray is confirmed, using an experimental setup based on an array of microelectrodes with analog integrated circuits.

We have investigated the pretilt angle of liquid crystal (LC) molecules induced by photo-alignment films of polyimide (Azo-PI) containing azobenzene in the backbone structure. To generate finite pretilt angles, the Azo-PI film with inclined alignment of the backbone structure was prepared by a double light-exposure method. In this method the corresponding polyamic acid (Azo-PAA) film was first exposed to linearly polarized ultraviolet/visible (UV/VIS) light (LP-light) at normal incidence, and then oblique angle irradiation of unpolarized UV/VIS light (UP-light) was performed in the plane of incidence perpendicular to the polarization direction of the LP-light. Repeated photo-isomerization reactions of azobenzene induce the alignment of the Azo-PAA backbone structure. By thermally imidizing the photo-treated film we obtained a thermally and optically stable Azo-PI film. The orientational distribution of the Azo-PI backbone structure was determined by measuring the polarized infrared absorption spectra as a function of the sample rotation angle and the angle of incidence. The pretilt angle of LC molecules was determined by a crystal rotation method. We found that the average inclination angle of the Azo-PI backbone structure increased with the UP-light exposure. The pretilt angle of LC molecules, measured from the surface plane, also increased with the UP-light exposure. We succeeded in generating a pretilt angle of 3. The relation between the LC pretilt angle and the average inclination angle of the Azo-PI backbone structure is discussed.

The use of coplanar waveguide (CPW)-fed ultra-wideband antennas in applications of multi-system integration has been demonstrated in this paper. Spiral slot antennas and feeding structures were fabricated on the same plane of the substrate so that the circuit process and the position alignment could be simplified. A CPW-fed spiral slot antenna possessing the ultra-wideband characteristic is also suitable for integration with a monolithic microwave integrated circuit (MMIC) module. Variations of the measured initial resonant frequency due to substrate thickness, number of turns and slot width are discussed in this paper. In addition, two topologies of the CPW-fed spiral slot antenna were devised and measured to demonstrate the capability of lowering the initial resonant frequency by adding a circularly microstrip stub at the end of the feedline and placing a short pin to terminate the spiral slot and feedline. According to the measured results, the CPW-fed spiral slot antenna covered most of the commercial wireless communication and satellite communication systems in radio frequency (RF), microwave and millimeter-wave applications.

Active Reliable Multicast (ARM) is a novel loss recovery scheme for large-scale reliable multicast that employs active routers to protect the sender and network bandwidth from unnecessary feedback and repair traffic. Active routers perform NACKs suppression, cache multicast data for local loss recovery, and use scoped retransmission to avoid exposure. Limited active resources at routers need to be optimized to achieve low loss recovery latency and/or high network throughput. In this paper, we study the cache placement strategies and caching policies for ARM. Several heuristics, namely uniform allocation, proportional allocation, max-min fair share and weighted allocation for cache allocation methods are proposed. To further improve the loss recovery performance, caching policies can be employed in conjunction with the cache allocation strategies. Several caching policies, namely complete caching, random caching and deterministic caching, are proposed. Extensive simulation experiments are conducted to evaluate and compare the performance of the proposed strategies and policies. Numerical results reveal that significant performance gains can be achieved when a proper cache placement strategy and a caching policy are used for a given available cache resource. Another interesting finding is that the contributions of the cache placement scheme and caching policy to the recovery latency performance are roughly independent. The obtained insights in this study will provide some design guidelines for optimal active resource allocation and caching polices for reliable multicast communications.

This paper presents circuit techniques using pulse-width and pulse-phase modulation (PWM/PPM) approaches for VLSI implementation of nonlinear dynamical systems. The proposed circuits implement discrete-time continuous-state dynamics by means of analog processing in a time domain, and also approximately implement continuous-time dynamics. Arbitrary nonlinear transformation functions are generated by the process in which a PPM signal samples a voltage or current source whose waveform in the time domain has the same shape as the desired transformation function. Because a shared arbitrary nonlinear voltage or current waveform generator can be constructed by digital circuits and D/A converters, high flexibility and real-time controllability are achieved. By using one of these new techniques, we have designed and fabricated a CMOS chaos circuit with arbitrary 1-D maps using a 0.6 µm CMOS process, and demonstrate from the experimental results that the new chaos circuit successfully generated various chaos with 7.5-7.8 bit precision by using logistic, tent and chaotic-neuron maps.

In this paper, we present a hierarchical multi-chip architecture which employs fully digital and word-parallel associative memories based on Hamming distance. High capacity scalability is critically important for associative memories since the required database capacity depends on the various applications. A multi-chip structure is most efficient for the capacity scalability as well as the standard memories, however, it is difficult for the conventional nearest-match associative memories. The present digital implementation is capable of detecting all the template data in order of the exact Hamming distance. Therefore, a hierarchical multi-chip structure is simply realized by using extra register buffers and an inter-chip pipelined priority decision circuit hierarchically embedded in multiple chips. It achieves fully chip- and word-parallel Hamming distance search with no throughput decrease, additional clock latency of O(log P), and inter-chip wires of O(P) in a P-chip structure. The feasibility of the architecture and circuit implementation has been demonstrated by post-layout simulations. The performance has been also estimated based on measurement results of a single-chip implementation.

The Hidden Markov Model (HMM) is a popular statistical framework for modeling and analyzing stochastic signals. In this paper, a novel strategy is proposed that makes use of level-building algorithm with a chain of AdaBoost HMM classifiers to model long stochastic processes. AdaBoost HMM classifier belongs to the class of multiple-HMM classifier. It is specially trained to identify samples with erratic distributions. By connecting the AdaBoost HMM classifiers, processes of arbitrary length can be modeled. A probability trellis is created to store the accumulated probabilities, starting frames and indices of each reference model. By backtracking the trellis, a sequence of best-matched AdaBoost HMM classifiers can be decoded. The proposed method is applied to visual speech processing. A selected number of words and phrases are decomposed into sequences of visual speech units using both the proposed strategy and the conventional level-building on HMM method. Experimental results show that the proposed strategy is able to more accurately decompose words/phrases in visual speech than the conventional approach.