This paper proposes a new maximal ratio combining (MRC) frequency diversity automatic-repeat-request (ARQ) scheme suitable for high-speed orthogonal frequency division multiplexing (OFDM) systems that is based on the conventional packet combining ARQ scheme. The proposed scheme regularly changes the previously prepared subcarrier assignment pattern at each retransmission according to the number of retransmissions. This scheme sharply reduces the number of ARQ retransmissions and much improves the throughput performance in slow fading environments by virtue of the frequency diversity effect while it requires no complex adaptive operations. Computer simulation results show that the proposed scheme reduces the required number of retransmissions to about 3 at the accumulative correct packet reception rate (ACPRR) of 0.9.

In this paper, the Linear Exponential Quadratic Gaussian with Loop Transfer Recovery (LEQG/LTR) methodology is employed for the design of high performance induction motor servo systems. In addition, we design a speed sensorless induction motor vector controlled driver with both the extended Kalman filter and the LEQG/LTR algorithm. The experimental realization of an induction servo system is given. Compared with the traditional PI and LQG/LTR methods, it can be seen that the system output sensitivity for parameter variations and the rising time for larger command input of the proposed method can be significantly reduced.

Image coding with vector quantization (VQ) reveals several defects which include edge degradation and high encoding complexity. This paper presents an edge-preserving coding system based on VQ to overcome these defects. A signal processing unit first classifies image blocks into low-activity or high-activity class. A high-activity block is then decomposed into a smoothing factor, a bit-plane and a smoother (lower variance) block. These outputs can be more efficiently encoded by VQ with lower distortion. A set of visual patterns is used to encode the bit-planes by binary vector quantization. We also develop a modified search-order coding to further reduce the redundancy of quantization indexes. Simulation results show that the proposed algorithm achieves much better perceptual quality with higher compression ratio and significant lower computational complexity, as compared to the direct VQ.

A selectively grown Si1-xGex base heterojunction bipolar transistor (HBT) was fabricated, and effects of Ge and B profiles on the device performance were investigated. Since no obvious leakage current was observed, it is shown that good crystallinity of Si1-xGex was achieved by using a UHV/CVD system with high-pressure H2 pre-cleaning of the substrate. Very high current gain of 29,000 was obtained in an HBT with a uniform Ge profile by both increasing electron injection from the emitter to the base and reducing band gap energy in the base. Since the Early voltage is affected by the grading of Ge content in the base, the HBT with the graded Ge profile provides very high Early voltage. However, the breakdown voltage is degraded by increasing Ge content because of reducing bandgap energy and changing dopant profile. To increase the cutoff frequency, dopant diffusion must be suppressed, and carrier acceleration by the internal drift field with the graded Ge profile has an additional effect. By doing them, an extremely high cutoff frequency of 130 GHz was obtained in HBT with graded Ge profiles.

In this paper, we present a traffic scheduling algorithm, called the Delay-Bound Monotonic with Average Rate Reservation (DM/ARR), which generates minimum output burstiness streams. We assume that connection i is policed by the leaky bucket algorithm with parameters (σi,ρi) where σi is the bucket size (or burstiness) and ρi is the leaky rate. Compared with the totally isolated scheme where connection i is allocated a bandwidth ri=max{σi/di,ρi} (di is the delay bound requirement of connection i), the DM/ARR algorithm has a better performance in the sense that it has a larger admission region. We prove that, among all possible scheduling algorithms that satisfy the delay bound requirements of established connections, DM/ARR results in the minimum output burstiness. This is important because a smaller burstiness implies a smoother traffic and thus the receiver (or next switch node in a multihop network) can handle it more easily. Numerical results show that the admission region of the DM/ARR algorithm is close to that of the earliest deadline first algorithm. A packetized version is studied for ATM networks.

RSPICE, a fast timing simulator for large digital MOS circuits, is presented in this paper. A new table-based region-wise linear MOS transistor model and the analytical solution of the generic sub-circuit primitive are applied to calculate the transient response of digital MOS circuits. The body effect of pass transistors is included in the MOS model and the floating capacitor network can be handled by this sub-circuit primitive as well. In RSPICE, MOS transistors with a DC path are grouped into a DC-connected block (DCCB), and DCCBs with a feedback path are combined as a strongly connected component (SCC). RSPICE orders SCCs by Tarjan's algorithm and simulates ordered SCCs one by one. DCCBs are basic cells in RSPICE and any DCCB can be mapped into one or more sub-circuit primitives. In order to calculate the transient response of these primitives analytically, RSPICE approximates the input signals of the primitive by piecewise linear functions. To compromise the simulation accuracy and run time, partial waveform and partial time convergent (PWPTC) combined with dynamic windowing technique is applied to simulate SCCs. Other key issues of RSPICE, such as circuit partition, pass-transistor and floating-capacitor processing, simulation-flow control and waveform modification are also discussed in detail. Compared with HSPICE , the simulation result of RSPICE is very accurate with an error less than 3%, but the speed is 1-2 orders over HSPICE.

The paper argues that a radical shift in the market for communications services is emerging, driven by the mass availability of cheap bandwidth, computing and global mobility combined with the pervasive rise of Internet based data services. At the same time, the Operation Support Systems (OSS's*) that are essential in order to create business value from these technologies are lagging behind market need. The authors argue for a re-think of the humble management system into a complete software wrap-around of the network to deliver a value creation platform - as different from yesterday's OSS as the bakelite telephone is from today's tri-band mobile handsets. This software will be based on product standards, not paper ones and will require a major shift of gears from the position of today. This value creation platform will be built from advanced, component based software delivered through a very different market model to that of today. Much of this technology exists; we simply need critical mass behind a common approach. The discussion in this paper represents the personal views of the authors and does not necessarily represent the views of any organisation.

A procedure for radar target discrimination is presented in this paper. The scheme includes an enhancement of late-time noisy scattering data based on a proposed signal processing algorithm and a decision procedure using previously known resonance annihilation filters. The signal processing stage is specifically adapted to scattering signals and makes use of the results of the singularity expansion method. It is based on a signal reconstruction using the SVD of a data matrix with a suitable choice of the number of singular vectors employed. To justify the inclusion of this stage, this procedure is shown to maintain the signal characteristics necessary to identify the scattered response. Simulation results clearly reveal a significant improvement due to the inclusion of the proposed stage. This improvement becomes especially important when the noise level is high or the targets to be discriminated (five regular polygonal loops) have a similar geometry.

An approximate formula is proposed for the equivalent susceptance of a circular iris in a parallel plate waveguide when the TEM mode cylindrical wave is incident from the center of the iris. Schwinger's variational method for a linear iris is generalized to the cylindrical case, and an approximate closed form formula is obtained which recovers the result of the linear iris when the radius of the circular iris is sufficiently larger than the wavelength. For verification of the formula, an exact integral equation is formulated and solved numerically by Galerkin's method. A comparison between them shows good agreement.

Internet communication is increasingly becoming an important element in daily life. Keeping this network safe from malicious elements is an urgent task for network management. To maintain the security level networks are generally, monitored for indications of usage with ill-intentions. Such indications are events which need to be collated, correlated and analyzed in real-time to be effective. However, on an average medium to large size network the number of such events are very large. This makes it practically impossible to analyze the information in real-time and provide the necessary security measures. In this paper, we propose a mechanism that keeps the number of events, to be analyzed, low thereby making it possible to provide ample security measures. We discuss a real-time Intrusion Detection System (IDS) for detecting network attacks. The system looks out for TCP ACK/RST packets, which are generally caused by network scans. The system can extract the tendency of network flows in real-time, based on the newly developed time-based clustering and Dynamic Access Tree creation techniques. The algorithm, implemented and deployed on a medium size backbone network using RMON (Remote MONitoring) technology, successfully detected 195 intrusion attempts during a one month period. The results of the pilot deployment are discussed. In this paper, the proposal, implementation and evaluation will be described.

For backup of failed VPs (Virtual Paths) in ATM (Asynchronous Transfer Mode) networks, many self-healing algorithms have already been proposed. However, since the existing algorithms recover each failed VP with a single backup VP, a problem arises in that those algorithms cannot necessarily provide a failed VP having a higher recovery priority with a larger recovery ratio, which is the ratio of the bandwidth of a backup VP to that of a failed VP. For a solution to the problem, this paper proposes a new self-healing algorithm which recovers each failed VP with one or more backup VPs. We also evaluate its availability by comparing with an existing algorithm through simulations.

This letter is concerned with a new algorithm which can be used to design a time-domain equalizer (TEQ) for xDSL systems employing the discrete multitone (DMT) modulation. The proposed algorithm, derived by neglecting the terms which do not affect the performance of a DMT system in ARMA modeling, is shown to have a good performance compared with the previous TEQ algorithms even with a significantly lower computational complexity. In addition, the proposed algorithm does not require the channel impulse response or training sequence, since all processing is made only with the received data.

This paper proposes a hardware/software cosynthesis system for digital signal processor cores and a hardware/software partitioning algorithm which is one of the key issues for the system. The target processor has a VLIW-type core which can be composed of a processor kernel, multiple data memory buses (X-bus and Y-bus), hardware loop units, addressing units, and multiple functional units. The processor kernel includes five pipeline stages (RISC-type kernel) or three pipeline stages (DSP-type kernel). Given an application program written in the C language and a set of application data, the system synthesizes a processor core by selecting an appropriate kernel (RISC-type or DSP-type kernel) and required hardware units according to the application program/data and the hardware costs. The system also generates the object code for the application program and a software environment (compiler and simulator) for the processor core. The experimental results demonstrate that the system synthesizes processor cores effectively according to the features of an application program and the synthesized processor cores execute most application programs with the minimum number of clock cycles compared with several existing processors.

A new feature parameter based on a discrete wavelet transform is proposed for word boundary detection of isolated utterances. The sum of standard deviation of wavelet coefficients in the third coarse and weighted first detailed scale is defined as a new feature parameter for endpoint detection. Experimental results demonstrate the superiority of the proposed feature to the conventional ones in capturing word boundaries even in noisy speech.

Given a Petri net PN=(P, T, E), a siphon is a set S of places such that the set of input transitions to S is included in the set of output transitions from S. Concerning extraction of minimal siphons containing a given specified set Q of places, the paper proposes three algorithms based on branch-and-bound method for enumerating, if any, all minimal siphons containing Q, as well as for extracting such one minimal siphon.

We investigated the reflection of light caused by sharp bends in optical fiber experimentally. The position distribution of reflection power was measured using an OTDR and an OLCR. We found that the reflection power increased linearly as the logarithm of the bending loss increased, which agrees with expectation from a simple theoretical model. We believe that the light we observed was part of the leaked light, which was reflected between the primary and secondary coatings.

A new flip-flop configuration for half-swing clocking is proposed to save total clocking power. In the proposed scheme, only NMOS's are clocked with the half-swing clock in order to make it operate without level converters or any additional logics which were used in the earlier half-swing clocking schemes. Vcc is supplied to the random logic circuits and flip-flops while Vcc/2 is supplied to the clock network and some parts of the flip-flop to reduce the power consumed in the clock network. Compared to the conventional scheme, the proposed flip-flop configuration can save the clocking power by 40%.

The glottal closure instants (GCIs) obtained from the wavelet analysis of speech signal are investigated in comparison with those obtained from the EGG signal. Experimental results have shown that about 96% of GCIs with wavelet transformed speech signal is located within 0.5 ms with respect to the GCIs with EGG signal.

The complexity of designing communication protocols has lead researchers to develop various techniques for designing and verifying protocols. One of the most important techniques is a compositional technique. Using a compositional technique, a large and complex protocol is designed and verified by composing small and simple protocols which are easy to handle, design and verify. Unlike the other compositional approaches, we propose compositional techniques for simultaneously composing service specifications and protocol specifications based on Formal Description Techniques (FDTs) called LOTOS. The proposed techniques consider alternative, sequential, interrupt and parallel composition of service specifications and protocol specifications. The composite service specification and the composite protocol specification preserve the original behaviour and the correctness properties of individual service specifications and protocol specifications. We use the weak bisimulation equivalence (), to represent the correctness properties between the service specification and the protocol specification. When a protocol specification is weak bisimulation equivalent to a service specification, the protocol satisfies all the logical properties of a communication protocol as well as provides the services that are specified in the service specification.

This paper deals with two-processor scheduling for a class of program nets, that are acyclic and SWITCH-less, and of which each node has unity node firing time. Firstly, we introduce a hybrid priority list L* that generates optimal schedules for the nets whose AND-nodes possess at most single input edge. Then we extend L* to suit for general program nets to give a new priority list L**. Finally, we use genetic algorithm to do the performance evaluation for the schedules generated by L** and show these schedules are quite close to optimal ones.