Design automation of LCD driver circuits is not sophisticatedly established. Display fineness of an LCD panel depends on a performance metric, ratio of pixel voltage to video voltage (RPV). However, there are several other important metrics, such as area, and the best circuit cannot be decided uniquely. This paper proposes a design automation technique for a LCD column driver to provide several circuit design results with different performance so that designers can select an appropriate design among them. The proposed technique is evaluated with an actual design data, and experimental results show that the proposed method successfully performs technology migration by transistor sizing. Also, the proposed technique is experimentally verified from points of solution quality and computational time.

The power reduction of display devices has become an important issue for extending battery life and running time when they are used in digital multimedia broadcasting (DMB) mobile phones. DMB mobile phones generally use 16-bit data per pixel to reduce power consumption even though a liquid crystal display (LCD) graphic controller can support 16-, 18-, and 24-bit data per pixel. Also, the total transmission time of 16-bit data per pixel is only half that for 18- and 24-bit data per pixel. Decoded 24-bit image data in the frame memory of a DMB decoder are asymmetrically truncated to 16-bit image data. This results in a lack of smoothness such as blocking effects and/or pseudo edge artifacts. To solve these problems, the author proposes and implements a new asymmetric pixel data truncation error compensation algorithm using 1-bit least significant bit (LSB) data expansion with correlated color information for the purpose of ensuring smoothness. In the experimental results, the proposed algorithm is able to correct various artifacts.

In this paper a new MOS charge pump architecture is presented, where a clock generator is used in each pump stage of the charge pump circuit to elevate voltage exponentially with stages. This charge pump with a clock level shifter is designed to run at an optimized operation frequency, which can make an excellent compromise between the rise time and the dynamic power dissipation. With less stages than the linear-cascade circuit, the power dissipation and the area of the novel charge pump circuit are markedly decreased. The simulating comparison results based on 1.2 µm CMOS, p-substrate double-poly double-metal process parameters show that the nonlinear charge pump with a high pumping efficiency can supply a steady 1 mA, 16 v output for portable LCDs.

An LCD Driver IC includes more than 300 buffer amplifiers on a single chip. The phase compensation capacitors (on-chip Miller capacitors) for the amplifiers are more than 1000 pF and occupy a large chip area. This paper describes a two-gain-stage amplifier in which an on-chip Miller capacitor is not used for phase compensation in an LCD Driver IC. In the proposed amplifier, phase compensation is achieved only by a newly introduced zero, which is formed by the load capacitance and a phase compensation resistor connected between the output of the amplifier and the capacitive load. Designs of the phase compensation resistor and the amplifier before compensation are discussed, considering a typical load capacitance range. The test chip was fabricated. The newly introduced zero successfully stabilized the amplifier. The chip area for the amplifier was reduced by 30-40%, compared with our previously reported one. The current consumption of the amplifier was only 5 µA. The experimental results of the fabricated test chip support that the proposed amplifier is suitable to an LCD driver IC with a smaller chip area.

This paper describes an efficient slew rate enhancement technique especially suitable for an operational amplifier used in an LCD driver IC. This technique employs an input-dependent biasing without directly monitoring an input; instead, monitoring an output of the first stage of the amplifier. This enhancement technique is easily applied to a conventional two-stage operational amplifier and requires only 8 additional transistors to increase slew rates for both rising and falling edges. The bias currents of the first and the second stages are simultaneously controlled by this biasing. Experimental operational amplifiers with and without this enhancement have been fabricated to demonstrate the improvement of slew rate. Slew rates of 12.5V/µsec for the rising edge and 50V/µsec for the falling edge with a 100 pF load capacitance have been achieved by this technique, compared with slew rates of 0.3V/µsec for the rising edge and 5V/µsec for the falling edge in the conventional amplifier.

This paper describes a segment driver IC for high-quality liquid-crystal-displays (LCDs). Major design issues in the segment driver IC are a wide signal bandwidth and excessive output-offset variation both within a chip and between chips. After clarifying the trade-off relation between the signal bandwidth and the output-offset variation originated from conventional sample-and-hold (S/H) circuits, two wide-band S/H circuits with low output-offset variation have been introduced. The basic ideas for the proposed S/H circuits are to improve timing of the sampling pulses applied to MOS analog switches and to prevent channel charge injection onto a storage capacitor when the switches turn off. The inter-chip offset-cancellation technique has been also introduced by using an additional S/H circuit. Two test chips were implemented using the above S/H circuits for demonstration purposes. The intra-chip output-offset standard deviation of 9.5 mVrms with a 3dB bandwidth of 50 MHz was achieved. The inter-chip output-offset standard deviation was reduced to 5.1 mVrms by using the inter-chip offset-cancellation technique. The evaluation of picture quality of an LCD using the chips shows the applicability of the proposed approaches to displays used for multimedia applications.