An H.264/AVC encoder LSI (named “SARA”) that supports High422 profile, as well as 422 profile of MPEG-2, has been developed for HDTV broadcasting infrastructures. It contains three motion estimation and compensation (ME/MC) engines with wide search ranges of -217.75 to +199.75 horizontally, -109.75 to +145.75 vertically, which can utilize almost all H.264/AVC ME/MC coding tools, such as multiple reference frame, variable block size, quarter-pel prediction, macroblock adaptive field/frame prediction (MBAFF), spatial/temporal direct mode, and weighted prediction. Our evaluations show that it can encode fast moving scenes with 1.2 dB to 1.7 dB higher than the JM. It was successfully fabricated in a 90-nm technology, and integrates 140 million transistors.

The message passing interface (MPI) broadcast communication commonly causes a severe performance bottleneck in multicore system that uses distributed memory. Thus, in this paper, we propose a novel algorithm and hardware structure for the MPI broadcast communication to reduce the bottleneck situation. The transmission order is set based on the state of each processing node that comprises the multicore system, so the novel algorithm minimizes the performance degradation caused by conflict. The proposed scoreboard MPI unit is evaluated by modeling it with SystemC and implemented using VerilogHDL. The size of the proposed scoreboard MPI unit occupies less than 1.03% of the whole chip, and it yields a highly improved performance up to 75.48% as its maximum with 16 processing nodes. Hence, with respect to low-cost design and scalability, this scoreboard MPI unit is particularly useful towards increasing overall performance of the embedded MPSoC.

We propose an improved TDoA (Time Difference of Arrival) localization scheme based on PSO (Particle Swarm Optimization) in UWB (Ultra Wide Band) systems. The proposed scheme is composed of two steps: the re-estimation of TDoA parameters and the re-localization of tag position. In both steps, the PSO algorithm is employed to improve the performance. In the first step, the proposed scheme re-estimates the TDoA parameters obtained by traditional TDoA localization to reduce the TDoA estimation error. In the second step, the proposed scheme with the TDoA parameters estimated in the first step, re-localizes the tag to minimize the location error. Simulation results show that the proposed scheme achieves better location performance than the traditional TDoA localization in various channel environments.

In this paper, we propose a novel low-cost Message Passing Interface (MPI) unit between processor nodes, which supports message passing in multiprocessor systems using distributed memory architecture. Our MPI unit operates in the standard mode – using the buffered mode for small amounts of data transaction and the synchronous mode for large amounts of data transaction. This results in increased performance by reducing the control message transmission time for the small amount of data. We verified the performance with a simulator designed based on SystemC. Additionally, we designed the MPI unit using VerilogHDL, and we synthesized it with a synopsys design compiler. The proposed standard mode MPI unit shows a high performance even though the size of the MPI unit occupies less than 1% of the whole chip. Thus, with respect to low-cost design and scalability, this MPI hardware unit is useful to increase overall performance of the embedded Multiprocessor System on a Chip (MPSoC).

We present a hardware sharing method for design space exploration of multi-processor embedded systems. In our prior work, we had developed a system-level design tool named SystemBuilder which automatically synthesizes target implementation of a system from a functional description. In this work, we have extended SystemBuilder so that it can automatically synthesize an area-efficient implementation which shares a hardware module among different applications. With SystemBuilder, designers only need to enable an option in order to share a hardware module. The designers, therefore, can easily explore a design space including hardware sharing in short time. A case study shows the effectiveness of the hardware sharing on design space exploration.

Parameter variations reveal themselves as different frequency and leakage powers per instances of the same MPSoC. By the increasing variation with technology scaling, worst-case-based scheduling algorithms result in either increasingly less optimal schedules or otherwise more lost yield. To address this problem, this paper introduces a variation-aware task and communication scheduling algorithm for multiprocessor system-on-chip (MPSoC). We consider both delay and leakage power variations during the process of finding the best schedule so that leakier processors are less utilized and can be more frequently put in sleep mode to reduce power. Our algorithm takes advantage of event tables to accelerate the statistical timing and power analysis. We use genetic algorithm to find the best schedule that maximizes power-yield under a performance-yield constraint. Experimental results on real world benchmarks show that our proposed algorithm achieves 16.6% power-yield improvement on average over deterministic worst-case-based scheduling.

The aim of this research is to study the power energy cost reduction of the mobile telecom industry through the supervisor control and data acquisition (SCADA) system application during globalization and liberalization competition. Yet this management system can be proposed functions: operating monitors, the analysis on load characteristics and dropping the cost of management.

To achieve an automated implementation for the application-specific heterogeneous multiprocessor systems-on-chip (MPSoC), partitioning and mapping the sequential programs onto multiple parallel processors is one of the most difficult challenges. However, the existing traditional parallelizing techniques cannot solve the MPSoC-related problems effectively, so designers are still required to manually extract the concurrency potentials in the program. To solve this bottleneck, an automated application partition technique is needed. However, completely automatic parallelism is ineffective, so it is promising to explore concurrency for certain practical special structures. To settle those issues, this paper proposes a template-based algorithm to automatically partition a special load-compute-store (LCS) loop structure. Since specific-instruction customization for the application specific instruction-set processors (ASIPs) has interactions with task partitioning, the proposed algorithm integrates the dynamic pipelining and ASIP techniques using an iterative improvement strategy: first, an initial pipelining scheme is generated to obtain the maximum parallelism; second, under the primary partition results specific instructions are customized respectively for each subprogram; third, the program is repartitioned via pipelining under the specific instruction configurations. The proposed method has been implemented in the context of a commercial extensible multiprocessor design flow, using the Xtensa-based XTMP platform from Tensilica Inc. Based on a case study of Fast Fourier Transform (FFT), the experimental results indicate that the partitioned programs by the proposed method demonstrate an average speedup of 10 compared to the original sequential programs which have not been partitioned and run on the uniprocessor system.

Programming the multiprocessor system-on-chip (MPSoC) requires partitioning the sequential reference programs onto multiple processors running in parallel. However, designers still need to partition the code manually due to the lack of automated partition techniques. To settle this issue, this paper proposes a partition exploration algorithm based on the search space smoothing techniques, and implements the proposed method using a commercial extensible processor (Xtensa LX2 processor from Tensilica Inc.). We have verified the feasibility of the algorithm by implementing the MPEG2 benchmark on the Xtensa-based two-processor system. The final experimental results indicate a performance improvement of at least 1.6 compared to the single-processor system.

The chaotic search is introduced into Quantum-behaved Particle Swarm Optimization (QPSO) to increase the diversity of the swarm in the latter period of the search, so as to help the system escape from local optima. Taking full advantages of the characteristics of ergodicity and randomicity of chaotic variables, the chaotic search is carried out in the neighborhoods of the particles which are trapped into local optima. The experimental results on test functions show that QPSO with chaotic search outperforms the Particle Swarm Optimization (PSO) and QPSO.

The Multiple Access Interference (MAI) and the Multipath Fading (MPF) restrict the performance of Code-Division Multiple-Access (CDMA) systems. The Multiuser Detection (MUD) based on Particle Swarm Optimization algorithm (PSO) with Rake processing is proposed in this paper to overcome these obstacles, followed by full details of how to apply the Binary PSO MUD (BPSO-MUD) on a CDMA system. Simulations show that the BPSO-MUD has significantly better performance than the Conventional Detection (CD).

We have determined the thickness and optical constants (refractive index and extinction coefficient) of each layer in the multi-layer organic light emitting diode (OLED) devices based on phosphorescent platinum octaethyl porphine (PtOEP) using a phase modulated spectroscopic ellipsometer. The thickness of each layer estimated from the ellipsometric measurement is different from the thickness measured with quartz oscillator during the evaporation of organic materials. The deviation of total multi-layer thickness is about 5%, while the deviation in each of N, N'-bis(1-naphtyl)-N, N'-diphenyl-1,1'-biphenyl-4,4'-diamine (α-NPD) and aluminum tris 8-hydroxyquinoline (Alq3) layers is about 20-25%. Additionally the spectra of refractive index and extinction coefficient of Alq3 and α-NPD layers are different from those that are measured using the single layer films. These results are understood by penetration of organic material from the neighboring layers in the multi-layer structure devices.

A low-band spectrum envelope reconstruction method was tested to see if it could improve the sound quality of F0 modified speech with the PSOLA (Pitch Synchronous OverLap Add) method. In the conventional PSOLA method, the extracted spectrum envelope using a Hanning window with two-pitch-period length had no reliable information in the band of frequencies lower than the original F0. This problem causes sound degradation of the F0 modified speech when the F0 is shifted downward. In the proposed method, the low-band spectrum envelope was properly modified according to the F0 modification rate. The amplitude of the F0 harmonic components in the low-band were reproduced based on the spectral tilt of the spectrum envelope. Subjective listening tests suggest the proposed method yields improved sound quality than the conventional TD-PSOLA method when the downward modification rate exceeds 0.4 octave.

By a worst input (for the selection phase of Heapsort) of size n, we mean a heap of size n such that, if it is given to the selection phase of Heapsort, the number of movements of data is maximum among the numbers of movements for all heaps of size n. D. E. Knuth showed a special type of worst inputs which we will call the K-type heaps. His definition of K-type heaps was by the induction on the size n. We give one characterization of K-type worst heaps that is based on their tree structure. This characterization gives more information on the tree structure of K-type heaps than the Knuth's definition.

In the paper, a theoretical and experimental investigation of a new type of the in-line optical fiber ellipsometer is described. The discussed device, based on the Sagnac interferometer, has the possibility to detect the changes of full polarisation state. The detection of the polarisation state in real time by a system containing standard single-mode fiber and an appropriate applied modulation technique is a new system property. The device uses interferometric measurement technique based on the fourth Fresnel-Arago's condition, which secures very good system accuracy and stability, also presented in the paper.