A new software based in-situ training (SBIST) method to achieve high accuracies is proposed for binarized neural networks inference accelerator chips in which measured offsets in sense amplifiers (activation binarizers) are transformed into biases in the training software. To expedite this individual training, the initial values for the weights are taken from results of a common forming training process which is conducted in advance by using the offset fluctuation distribution averaged over the fabrication line. SPICE simulation inference results for the accelerator predict that the accuracy recovers to higher than 90% even when the amplifier offset is as large as 40mV only after a few epochs of the individual training.

In recent years, deep neural network (DNN) has achieved considerable results on many artificial intelligence tasks, e.g. natural language processing. However, the computation complexity of DNN is extremely high. Furthermore, the performance of traditional von Neumann computing architecture has been slowing down due to the memory wall problem. Processing in memory (PIM), which places computation within memory and reduces the data movement, breaks the memory wall. ReRAM PIM is thought to be a available architecture for DNN accelerators. In this work, a novel design of ReRAM neuromorphic system is proposed to process DNN fully in array efficiently. The binary ReRAM array is composed of 2T2R storage cells and current mirror sense amplifiers. A dummy BL reference scheme is proposed for reference voltage generation. A binary DNN (BDNN) model is then constructed and optimized on MNIST dataset. The model reaches a validation accuracy of 96.33% and is deployed to the ReRAM PIM system. Co-design model optimization method between hardware device and software algorithm is proposed with the idea of utilizing hardware variance information as uncertainness in optimization procedure. This method is analyzed to achieve feasible hardware design and generalizable model. Deployed with such co-design model, ReRAM array processes DNN with high robustness against fabrication fluctuation.

An efficient resistive random access memory (ReRAM) structure is developed for accelerating convolutional neural network (CNN) powered by the in-memory computation. A novel ReRAM cell circuit is designed with two-directional (2-D) accessibility. The entire memory system is organized as a 2-D array, in which specific memory cells can be identically accessed by both of column- and row-locality. For the in-memory computations of CNNs, only relevant cells in an identical sub-array are accessed by 2-D read-out operations, which is hardly implemented by conventional ReRAM cells. In this manner, the redundant access (column or row) of the conventional ReRAM structures is prevented to eliminated the unnecessary data movement when CNNs are processed in-memory. From the simulation results, the energy and bandwidth efficiency of the proposed memory structure are 1.4x and 5x of a state-of-the-art ReRAM architecture, respectively.

Several new memories are being studied as candidates of future DRAM that seems difficult to be scaled. However, the read signal in these new memories needs to be amplified in a single-end manner with reference signal supplied if they are aimed for being applied to the high-density main memory. This scheme, which is fortunately not necessary in DRAM's 1/2Vdd pre-charge sense amp, can become a serious bottleneck in the new memory development, because the device electrical parameters in these new memory cells are prone to large cell-to-cell variations without exception. Furthermore, the extent to which the parameter fluctuates in data “1” is generally not the same as in data “0”. In these situations, a new sensing scheme is proposed that can minimize the sensing error rate for high-density single-end emerging memories like STT-MRAM, ReRAM and PCRAM. The scheme is based on averaging multiple dummy cell pairs that are written “1” and “0” in a weighted manner according to the fluctuation unbalance between “1” and “0”. A detailed analysis shows that this scheme is effective in designing 128Mb 1T1MTJ STT-MRAM with the results that the required TMR ratio of an MTJ can be relaxed from 130% to 90% for the fluctuation of 6% sigma-to-average ratio of MTJ resistance in a 16 pair-dummy cell averaging case by using this technology when compared with the arithmetic averaging method.

We have studied the formation of Ti-nanodots (NDs) by remote H2 plasma (H2-RP) exposure and investigated how the embedding of Ti-NDs affects the resistive switching properties of Si-rich oxides (SiOx) because it is expected that NDs will trigger the formation of the conductive filament path in SiOx. Ti-NDs with an areal density as high as 1011 cm-2 were fabricated by exposing a Ge/Ti stacked layer to the H2-RP without external heating, and changes in the chemical structure of Ge/Ti stacked layer with the Ti-NDs formation were evaluated by using hard x-ray photoemission spectroscopy (HAXPES) and x-ray photoelectron spectroscopy (XPS). Resistive switching behaviors of SiOx with Ti-NDs were measured from current-voltage curves and compared to the results obtained from samples of SiOx with a Ti thin layer.

Ni nanodots (NDs) used as nano-scale top electrodes were formed on a 10-nm-thick Si-rich oxide (SiO$_{mathrm{x}}$)/Ni bottom electrode by exposing a 2-nm-thick Ni layer to remote H$_{2}$-plasma (H$_{2}$-RP) without external heating, and the resistance-switching behaviors of SiO$_{mathrm{x}}$ were investigated from current-voltage ( extit{I--V}) curves. Atomic force microscope (AFM) analyses confirmed the formation of electrically isolated Ni NDs as a result of surface migration and agglomeration of Ni atoms promoted by the surface recombination of H radicals. From local extit{I--V} measurements performed by contacting a single Ni ND as a top electrode with a Rh coated Si cantilever, a distinct uni-polar type resistance switching behavior was observed repeatedly despite an average contact area between the Ni ND and the SiO$_{mathrm{x}}$ as small as $sim$ 1.9 $ imes$ 10$^{-12}$cm$^{2}$. This local extit{I--V} measurement technique is quite a simple method to evaluate the size scalability of switching properties.

We have investigated the impact of O2 annealing after SiOx deposition on the switching behavior to gain a better understanding of the resistance switching mechanism, especially the role of oxygen deficiency in the SiOx network. Although resistive random access memories (ReRAMs) with SiOx after 300 annealing sandwiched with Pt electrodes showed uni-polar type resistance switching characteristics, the switching behaviors were barely detectable for the samples after annealing at temperatures over 500. Taking into account of the average oxygen content in the SiOx films evaluated by XPS measurements, oxygen vacancies in SiOx play an important role in resistance switching. Also, the results of conductive AFM measurements suggest that the formation and disruption of a conducting filament path are mainly responsible for the resistance switching behavior of SiOx.

We have fabricated Pt/Si-rich oxide (SiOx)/TiN stacked MIM diodes and studied an impact of the structural asymmetry on their resistive switching characteristics. XPS analyses show that a TiON interfacial layer was formed during the SiOx deposition on TiN by RF-sputtering in an Ar + O2 gas mixture. After the fabrication of Pt top electrodes on the SiOx layer, and followed by an electro-forming process, distinct bi-polar type resistive switching was confirmed. For the resistive switching from high to low resistance states so called SET process, there is no need to set the current compliance. Considering higher dielectric constant of TiON than SiOx, the interfacial TiON layer can contribute to regulate the current flow through the diode. The clockwise resistive switching, in which the reduction and oxidation (Red-Ox) reactions can occur near the TiN bottom electrode, shows lower RESET voltages and better switching endurance than the counter-clockwise switching where the Red-Ox reaction can take place near the top Pt electrode. The result implies a good repeatable nature of Red-Ox reactions at the interface between SiOx and TiON/TiN in consideration of relatively high diffusibility of oxygen atoms through Pt.

We have studied resistance-switching properties of RF sputtered Si-rich oxides sandwiching with Pt electrodes. By sweeping bias to the top Pt electrode, non-polar type resistance switching was observed after a forming process. In comparison to RF sputtered TiOx case, significant small current levels were obtained in both the high resistance state (HRS) and the low resistance state (LRS). And, even with decreasing SiOx thickness down to 8 nm from 40 nm, the ON/OFF ratio in resistance-switching between HRS and LRS as large as 103 was maintained. From the analysis of current-voltage characteristics for Pt/SiOx on p-type Si(100) and n-type Si(100), it is suggested that the red-ox (REDction and OXidation) reaction induced by electron fluence near the Pt/SiOx interface is of importance for obtaining the resistance-switching behavior.

Resistive switching of metal-insulator-metal (MIM), consisting of a metal-organic chemical vapour deposition (MOCVD) TiO2 layer sandwiched between Pt electrodes, has been measured systematically before and after thermal annealing in different ambiences. With H2 annealing at 400, the current level in the high-resistive state (HRS) significantly decreased while little change in the low-resistive state (LRS) was observed. As a result, the switching ratio over 7 orders of magnitude at the current level was obtained. From the analysis of current-voltage (I-V) characteristics in HRS and LRS, we found that the LRS was characterized with an ohmic conduction, while in the HRS after H2 annealing, charge trapping became significant as a result of a significant decrease in the current level. In a separate experiment, a partial reduction in TiO2 was detected using high-resolution X-ray photoelectron spectroscopy (XPS) after resistant-state switching from HRS to LRS by using a Hg probe as a top electrode, which is associated with filament formation.

Programmable Metallization Cell (PMC) Random Access Memory is based on the electrochemical growth and removal of nanoscale metallic pathways in thin films of solid electrolytes. In this study, we investigate the nature of thin films formed by the photo doping of Cu into chalcogenide materials for use in programmable metallization cell devices. These devices rely on metal ion transport in the film so produced to create electrically programmable resistance states. The results imply that a Cu-rich phase separates owing to the reaction of Cu with free atoms from chalcogenide materials.