In this paper, a cell-driven multiplier generator is developed that can produce high-performance gate-level netlists for multiplier-related arithmetic functional units, including multipliers, multiplier and accumulators (MAC) and dot product calculator. The generator optimizes the speed/area performance both in the partial product compression and in the final addition stage for the specified process technology. In addition to the conventional CMOS full adder cells, we have also designed fast compression elements based on pass-transistor logic for further performance improvement of the generated multipliers. Simulation results show that our proposed generator could produce better multiplier-related functional units compared to those generated using Synopsys Designware library or other previously proposed approaches.

An approach based on signal subspace analysis is proposed to blind estimation of the PN (Pseudo Noise) sequence from lower SNR (Signal to Noise Ratios) DS/SS (Direct Sequence Spread Spectrum) signals. The received signal is divided into vectors according to a temporal window, from which an autocorrelation matrix is computed and accumulated. The PN sequence can be reconstructed from principal eigenvectors of the matrix.

In this paper, we propose an OFDM scheme with pre-IDFT/DFT and the frequency domain equalization on frequency-selective Rayleigh fading channels. In this scheme, a two-dimensional block interleaving is used to randomize the correlated noise caused by the frequency domain linear equalizer. Then, the pre-DFT averages the interleaved noise enhancement and improves the error performance of the proposed scheme. Computer simulations confirm the bit error probability of the proposed scheme for multilevel modulations.

This paper presents a semi-automatic algorithm for video object segmentation. Our algorithm assumes the use of multiple key video frames in which a semantic object of interest is defined in advance with human assistance. For video frames between every two key frames, the specified video object is tracked and segmented automatically using Learning Vector Quantization (LVQ). Each pixel of a video frame is represented by a 5-dimensional feature vector integrating spatial and color information. We introduce a parameter K to adjust the balance of spatial and color information. Experimental results demonstrate that the algorithm can segment the video object consistently with less than 2% average error when the object is moving at a moderate speed.

Call admission control (CAC) plays a significant role in providing the efficient use of the limited bandwidth and the desired quality-of-service (QoS) in mobile multimedia communications. As efficiency is an important performance issue for CAC in the mobile networks with multimedia services, the concept of fairness among services should also be considered. Game theory provides an appropriate framework for formulating such fair and efficient CAC problem. Thus, in this paper, a framework based on game theory (both of noncooperative and cooperative games) is proposed to select fair-efficient guard bandwidth coefficients of the CAC scheme for the asymmetrical traffic case in mobile multimedia communications. The proposed game theoretic framework provides fairness and efficiency in the aspects of bandwidth utilization and QoS for multiple classes of traffic, and also guarantees the proper priority mechanism. Call classes are viewed as the players of a game. Utility function of the player is defined to be of two types, the bandwidth utilization and the weighted sum of new call accepting probability and handoff succeeding probability. The numerical results show that, for both types of the utility function, there is a unique equilibrium point of the noncooperative game for any given offered load. For the cooperative game, the arbitration schemes for the interpersonal comparisons of utility and the bargaining problem are investigated. The results also indicate that, for both types of the utility function, the Nash solution with the origin (0,0) as the starting point of the bargaining problem can achieve higher total utility than the previous CAC scheme while at the same time providing fairness by satisfying a set of fairness axioms. Since the Nash solution is determined from the domain of the Pareto boundary, the way to generate the Pareto boundary is also provided. Therefore, the Nash solution can be obtained easily.

In this paper, a low-voltage low-power sigma-delta modulator dedicated to implantable sensing devices is presented. This second-order single-loop sigma-delta modulator is implemented with half-delay integrators. These integrators are based on new fully-differential CMOS class AB switched-Operational Transconductance Amplifier (switched-OTA). An on-chip voltage doubler is introduced to locally boost a supply voltage at the input stage of a conventional OTA in order to allow rail-to-rail signal swing. Experimental results of the modulator fabricated in CMOS 0.18 µm technology confirm its expected features of a peak signal-to-noise ratio (SNR) of 72 dB, a signal-to-noise distortion ratio (SNDR) of 62 dB in a 5 kHz signal bandwidth, and a power consumption lower than 66 µW with a 900 mV voltage supply.

A scalable multicast session announcement system is a key component of a group communication framework over the Internet. It enables the announcement of session parameters (like the {source address; group address} pair) to a potentially large number of users, according to each site administrator's policy. This system should accommodate any flavor of group communication system, like the Any-Source Multicast (ASM) and Source-Specific Multicast (SSM) schemes. In this paper we first highlight the limitations of the current Session Announcement Protocol (SAP) and study several other information distribution protocols. This critical analysis leads us to formulate the requirements of an ideal multicast session announcement system. We then introduce a new session announcement system called "Channel Reflector". It appears as a hierarchical directory system and offers an effective policy and scope control technique. We finally mention some design aspects, like the protocol messages and configuration structures the Channel Reflector uses.

This letter discusses the prediction of the time-varying bit error rate (BER) for a transmitting channel using recent transmissions and retransmissions. Depending on the predicted BER, we propose a maximum frame size control to improve the goodput in wireless networks. It is shown, using simulation, that when the maximum frame size is controlled relative to the time-varying BER the goodput of the network is improved.

Zero-suppressed BDDs (ZBDDs) have been used in the nonenumerative path delay fault (PDF) grading of VLSI circuits. One basic and one cut-based grading algorithm are proposed to grade circuits with polynomial and exponential number of PDFs, respectively. In this article, we present a new ZBDD-based basic PDF grading algorithm to enable grading of some circuits with exponential number of PDFs without using the cut-based algorithm. The algorithm overcomes the memory overflow problems by dynamically pruning the ZBDD at run-time. This new algorithm may give exact or pessimistic coverage depending on the statuses of the pruned nodes. Furthermore, we re-assess the performance of the static variable ordering heuristics in ZBDDs for PDF coverage calculation. The proposed algorithm combined with the efficient static variable ordering heuristics can avoid ZBDD size explosion in many circuits. Experimental results for ISCAS85 benchmarks show that the proposed algorithm efficiently grades circuits.

When a dependency parser analyzes long sentences with fewer subjects than predicates, it is difficult for it to recognize which predicate governs which subject. To handle such syntactic ambiguity between subjects and predicates, we define an "a subject clause (s-clause)" as a group of words containing several predicates and their common subject. This paper proposes a two-phase method for S-clause segmentation. The first phase reduces the number of candidates of S-clause boundaries, and the second performs S-clause segmentation using decision trees. In experimental evaluation, the S-clause information turned out to be effective for determining the governor of a subject and that of a predicate in dependency parsing. Further syntactic analysis using S-clauses achieved an improvement in precision of 5 percent.

This paper proposes a cell layout synthesis technique to minimize the sensitivity to wiring faults due to spot defects. We modeled the sensitivity to faults on intra-cell routings with consideration to the spot defects size distribution and the end effect of critical areas. The effect of the sensitivity reduction on the yield is also discussed. By using the model as a cost function, we comprehensively generate the minimum width layout of CMOS logic cells and select the optimal layouts. Experimental results show that our technique reduces about 15% of the fault sensitivities compared with the wire-length-minimum layouts for benchmark CMOS logic circuits which have up to 14 transistors.

This paper presents a framework for automatic video region-of-interest determination based on visual attention model. We view this work as a preliminary step towards the solution of high-level semantic video analysis. Facing such a challenging issue, in this work, a set of attempts on using video attention features and knowledge of computational media aesthetics are made. The three types of visual attention features we used are intensity, color, and motion. Referring to aesthetic principles, these features are combined according to camera motion types on the basis of a new proposed video analysis unit, frame-segment. We conduct subjective experiments on several kinds of video data and demonstrate the effectiveness of the proposed framework.

In this paper, the 1-D real-valued discrete Gabor transform (RDGT) proposed in our previous work and its relationship with the complex-valued discrete Gabor transform (CDGT) are briefly reviewed. Block time-recursive RDGT algorithms for the efficient and fast computation of the 1-D RDGT coefficients and for the fast reconstruction of the original signal from the coefficients are then developed in both the critical sampling case and the oversampling case. Unified parallel lattice structures for the implementation of the algorithms are studied. And the computational complexity analysis and comparison show that the proposed algorithms provide a more efficient and faster approach for the computation of the discrete Gabor transforms.

This paper presents a VLSI processor for high-speed and reliable stereo matching based on adaptive window-size control of SAD(Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using multi-resolution images. Parallel memory access is essential for highly parallel image processing. For parallel memory access, this paper also presents an optimal memory allocation that minimizes the hardware amount under the condition of parallel memory access at specified resolutions.

Undersampling (or bandpass sampling) phase modulated signals directly at high frequency band, the harmful effects of the aperture jitter characteristics of ADCs (Analog-to-Digital converters) and sampling clock instability of the system can not be ignored. In communication systems the sampling jitter brings additional phase noise to the constellation pattern besides thermal noise, thus the BER (bit error rate) performance will be degraded. This paper examines the relationship between the input frequency to ADC and the sampling jitter in digital IF (Intermediate Frequency) downconversion receivers with undersampling scheme. This paper presents the measurement results with a real hardware prototype system as well as the computer simulation results with a theoretically modeled IF sampling receiver. We evaluated EVM (Error Vector Magnitude) in various clock jitter configurations with commonly used and reasonable cost ADCs of which sampling rates was 40 MHz. According to the results, the IF input frequencies of QPSK (16 QAM) signals were limited below around 290 (210) MHz for wireless LAN standard, and 730 (450) MHz for W-CDMA standard, respectively, in our best configuration.

Recent microprocessors have included SIMD (single instruction multiple data) extensions into their instruction set architecture to improve the performance of multimedia applications. SIMD instructions speed up the execution of programs but pose lots of challenges to software developers. An efficient matrix-based splitter (or merger), which can split an N N 2-D DCT block into four N/2 N/2 or two N N/2 (or N/2 N) 2-D DCT blocks (or merger small size blocks into a large size one), specialized for SIMD architectures is presented in this paper. The programming-level complexity of the proposed methods is lower than that of the direct approach. Furthermore, even without using SIMD instructions, the algorithmic-level complexity of the proposed DCT splitter/merger is still lower than that of the direct one and is the same as that of the most efficient approach existed in the literature. When N = 8, our method can be applied to act as a transcoder between the latest video coding standards AVC/H.264 and the older ones, such as MPEG-1, MPEG-2 and MPEG-4 part 2. We also provide the image quality tests to show the performance of the proposed 2-D DCT splitter and merger.

This letter proposes a run-length code based test data compression technique capable of efficient compression. The proposed test compression method is based on a hybrid run-length encoding, which greatly reduces test data storage on the tester. The code words are carefully selected so as to increase the compression ratio for the test data. Also, a heuristic mapping algorithm and a scan latch reordering method for don't care values in the test cubes increase the compression ratio. Results indicate that the proposed code and heuristic mapping schemes are very efficient in reducing test data. Reduced test data results in less test storage and test time.

As a specific signature, the nominative proxy signature scheme is a method in which the designated proxy signer generates a nominative signature and transmits it to a verifier, instead of the original signer. Recently, Seo et al. proposed a nominative proxy signature scheme for mobile communication and claimed that the scheme hash non-repudiation. However, after analyzing the scheme, we show that the scheme is insecure and cannot provide non-repudiation, note that a malicious original signer can forge the proxy signer to sign on any message. Finally, we also present a modification version of the scheme to repair the security flaw.

In this study, we have proposed an efficient automatic multilevel thresholding method for image segmentation. An effective criterion for measuring the separability of the homogenous objects in the image, based on discriminant analysis, has been introduced to automatically determine the number of thresholding levels to be performed. Then, by applying this discriminant criterion, the object regions with homogeneous illuminations in the image can be recursively and automatically thresholded into separate segmented images. The proposed method is fast and effective in analyzing and thresholding the histogram of the image. In order to conduct an equitable comparative performance evaluation of the proposed method with other thresholding methods, a combinatorial scheme is also introduced to properly reduce the computational complexity of performing multilevel thresholding. The experimental results demonstrated that the proposed method is feasible and computationally efficient in automatic multilevel thresholding for image segmentation.

With reference to video motion estimation in the framework of the new H.264/AVC video coding standard, this paper presents algorithmic and architectural solutions for the implementation of context-aware coprocessors in real-time, low-power embedded systems. A low-complexity context-aware controller is added to a conventional Full Search (FS) motion estimation engine. While the FS coprocessor is working, the context-aware controller extracts from the intermediate processing results information related to the input signal statistics in order to automatically configure the coprocessor itself in terms of search area size and number of reference frames; thus unnecessary computations and memory accesses can be avoided. The achieved complexity saving factor ranges from 2.2 to 25 depending on the input signal while keeping unaltered performance in terms of motion estimation accuracy. The increased efficiency is exploited both for (i) processing time reduction in case of software implementation on a programmable platform; (ii) power consumption reduction in case of dedicated hardware implementation in CMOS technology.