In this paper, we propose a circuit configuration for the low-frequency second-order active RC BPF (band pass filter) which has stable high Q. This proposed circuit is a high Q low-frequency one with a small capacitance, which is realized by applying an output capacitance multiplier to the circuit. Then a detailed circuit analysis is performed for the proposed circuit. From the simulation results of fo and Q for various combinations of circuit element values, we can confirm that the circuit realization of a center frequency of several Hz is possible by employing chip condensers of dozens of nF. The bread-board circuit of this configuration is confirmed to have small temperature dependences of fo and Q by the experiment. It is also clarified from detailed noise analysis and noise measurement that the circuit noise is sufficiently maintained at a low level.

Packet-recognition/code-acquisition (PR/CA) is one of the most important issues in packet communication systems. In a CDMA Unslotted ALOHA system, Multiple Access Interference (MAI) may bring about errors in PR/CA. The MAI mainly stems from already recognized packets and newly arriving packets under the execution of PR/CA. This characteristic of asynchronous transmission in CDMA U-ALOHA systems implies that only one or a few packets arrive at the receiver within a short interval of a execution. Furthermore, newly arriving packets are recognized and code-acquired by using a short preamble part. Consequently, the MAI from the packets under the execution of the PR/CA will be small. Focusing on that point, this paper proposes applying the IC scheme in order to suppress the MAI from the already recognized and code-acquired packets. A performance evaluation demonstrates that such an application is valid due to the small amount of MAI from the packets under the execution of PR/CA. In addition, we demonstrates that the scheme reduces false recognition rather than mis-recognition. Such a scheme improves the performance of not only PR/CA, but also the throughput.

A new technique called the Dual Parasitic Beam (DPB) technique is proposed to suppress grating lobes in a rectangular waveguide broad wall transverse slot array. This technique involves an extra layer of parasitic strip dipoles that generate the DPB to suppress the grating lobes without opposing the main beam of the original slot linear array. A full wave EM analysis in Method of Moments (MoM) is conducted to compute the coupling excitation coefficients as well as the far field patterns of the slot and dipole currents. Analysis shows that a suitable dimension and arrangement of dipoles are needed to get a desired level of dipole excitations to meet the grating suppression condition. It is found that the grating lobes can be suppressed as much as 15 dB in the presence of the parasitic dipoles. Experiments are conducted to confirm the computed results.

In order to miniaturize a very low-level dc current amplifier and to speed up its output response speed, we proposed to employ the switched-capacitor circuit (SCC) as its negative feedback circuit, instead of the conventionally used high-ohmage resistor. However, in the case of using SCC, the output waveform had unnecessary components. To decrease the effect of these components and to speed up the response speed, we used a switched-capacitor filter (SCF), an offset controller, and a positive feedback circuit. As a result, we demonstrated that it was useful to use the amplifier using the SCC.

The conditional sum adder (CSA) has been shown to outperform other adders applied in high-speed applications. This investigation proposes a modified CSA called the conditional carry adder (CCA). Based on the proposed adder architecture, six 64-bit hybrid dual-threshold CCAs for power-aware applications were discussed. Architectural modification of the CCA raises the operation speed, decreases the power dissipation, and lowers the hardware overhead. The proposed 64-bit CCA can decrease the number of multiplexers and internal nodes in the adder design by around 27% compared to the 64-bit CSA. Furthermore, components on critical paths use a low threshold voltage to accelerate the speed of operation, and other components use the normal threshold voltage to save power. This feature is very useful in implementing power-aware arithmetic systems. One of the proposed circuits has the lowest power-delay product and energy-delay product. The hybrid circuit represents a fine compromise between power and performance. Its power efficiency is better than that of the single threshold voltage circuit designs.

Larger object classes often become more costly classes in the maintenance phase of object-oriented software. Consequently class would have to be constructed in a medium or small size. In order to discuss such desirable size, this paper proposes a simple method for predictively discriminating costly classes in version-upgrades, using a class size metric, Stmts. Concretely, a threshold value of class size (in Stmts) is provided through empirical studies using many Java classes. The threshold value succeeded as a predictive discriminator for about 73% of the sample Java classes.

A folded loop antenna for handsets has already been introduced and shown as one of balance-fed antennas for handsets, which is very effective to mitigate the antenna performance degradation due to the body effect. In order to meet the requirements for the latest handsets such as low profile and small size, a folded loop antenna is modified. The antenna, which is possibly built in the handsets, is newly proposed. Low profile and small size is achieved by consisting of the half of low profile folded loop antenna, which has a structure folded loop elements sideways so that the antenna can be placed on the ground plane (GP). In the analysis, the electromagnetic simulator based on the FDTD (Finite Difference Time Domain) method is used and the design parameters useful in practical operation are found. The electromagnetic simulator based on the Method of Moment (MoM) is used to calculate the current distribution on the antenna element and the GP. An example of low profile and small size antenna which has wideband characteristics are designed based on these parameters, and the antenna characteristics such as VSWR, the current distributions and the radiation patterns are compared with Planar Inverted-F Antenna (PIFA), which is one of conventional built-in antennas for handset. As a result, it has been confirmed that the physical volume of the antenna, which has been introduced here, becomes smaller than that of PIFA. In addition, the radiation efficiency of these antennas is measured and the results are compared with each other.

A method for detecting shallowly buried landmines using sequential ground penetrating radar (GPR) data is presented. After removing a dominant coherent component arising from the ground surface reflection from the GPR data, three kinds of target features related to wave correlation, energy ratio, and signal arrival time are extracted. Since the detection problem treated here is reduced to a binary hypothesis test, an approach based on a likelihood ratio test is employed as a detection algorithm. In order to check the detection performance, a Monte Carlo simulation is carried out for data generated by a two-dimensional finite-difference time domain (FDTD) method. Results given in the form of receiver operating characteristic (ROC) curves show that good detection performance is obtained even for landmines buried at shallow depths under rough ground surfaces, where the responses from the landmines and that from the ground surface overlap in time.

A fully integrated broadband distributed frequency tripler, periodically loaded with HBV devices, has been designed and fabricated and has demonstrated the generation of a broad range of output frequencies of up to 570 GHz. Key to the design is the principle that the entire frequency tripler circuit is produced monolithically and incorporates novel HBV devices electrically and mechanically interconnected by a thin low-loss SU-8 membrane. With the device fabrication approach used, the novel HBV devices are able to produce a higher capacitance-voltage swing ratio whilst simultaneously minimizing the device series and contact resistances to achieve the optimum conversion efficiency. The entire concept of this work was to design a cost effective fully integrated waveguide package, with the frequency tripler circuit mounted at the E-plane of a micromachined waveguide which was constructed with stepped height and width to prevent the propagation of higher order modes inside the waveguide sections. The micromachined waveguide sections exhibit high dimensional accuracy and a good surface finish which is necessary for the efficient propagation of high frequency signals. The frequency tripler circuit and the accompanying micromachined waveguide sections are mounted in a specifically designed metal test fixture to form a compact and cost-effective subcomponent with great commercial potential for broadband harmonic generation of up to terahertz frequencies. This paper presents the design methodology and techniques used to produce the frequency tripler package, together with some initial measurement results.

This paper presents an analysis of the Slotted DS-CDMA system with modified node components in order to construct a load control structure in which the service rates of each node can be dynamically adapted without using feedback information. In contrast to the traditional Slotted DS-CDMA which is widely represented with single queue, prior emphasis of the approach is laid on the usage of an additional queue which is applied to manage the collided packet traffic while its queue size is also used as a load control parameter. Semi-Markov process is applied to describe the statistic behavior of the system in steady state. Trade-offs between two major performance parameters, i.e., delay and throughput, are presented and compared with those of the traditional system. Results obtained from the simulation and numerical analysis using queuing concept are compared. With these results, an advantage performance for group packets is shown, and we finally extend the concept based on the obtained results to describe a simple algorithm using one way control message as the tool to alleviate the stability problem.

Frequency domain blind source separation has the great advantage that the complicated convolution in time domain becomes multiple efficient multiplications in frequency domain. However, the inherent ambiguity of permutation of ICA becomes an important problem that the separated signals at different frequencies may be permuted in order. Mapping the separated signal at each frequency to a target source remains to be a difficult problem. In this paper, we first discuss the inter-frequency correlation based method, and propose a new method using the continuity in power between adjacent frequency components of same source. The proposed method also implicitly utilizes the information of inter-frequency correlation, as such has better performance than the previous method.

For the purpose of analyzing noise characteristics of a very low-level dc current amplifier using a high-ohmage resistor negative feedback circuit, we made some noise sources in the form of the electronic circuit simulation program PSpice with the C language program and simulated transient analyses of the very low-level dc current amplifier using the PSpice. As a result, it was observed that in terms of rise time and increases in the amplitudes of the noise voltage with or without positive feedback circuit, the behavior of output waveform of the simulated equivalent circuit was similar to that of the experimental circuit.

Mobile ad-hoc networks consist of mobile nodes interconnected by multihop path that has no fixed network infrastructure support. Due to the limited bandwidth and resource, and also the frequent changes in topologies, ad-hoc network should consider these features for the provision of security. We present a secure routing protocol based on identity-based signcryption scheme. Since the proposed protocol uses an identity-based cryptosystem, it does not need to maintain a public key directory and to exchange any certificate. In addition, the signcyption scheme simultaneously fulfills both the functions of digital signature and encryption. Therefore, our protocol can give savings in computation cost and have less amount of overhead than the other protocols based on RSA because it uses identity-based signcryption with pairing on elliptic curve. The effectiveness of our protocol is illustrated by simulations conducted using ns-2.

This paper presents a distributed task assignment algorithm in a logical unidirectional ring, which guarantees that almost all tasks are assigned to servers with the first come first served (FCFS) policy without a global clock. A task assignment for a process is obtained in the time period needed for a message to circle the ring. This time period is almost optimal for a unidirectional ring. The FCFS policy is very important in terms of task fairness and can also avoid starvation and provide an efficient response time. Simulation results show that the algorithm generally works better than conventional task assignment or load balancing schemes with respect to both mean response time and task fairness.

This paper proposes a genetic programming method to synthesize passive filter circuits. This method allows both the circuit topology and the component values to be evolved simultaneously. Experiments show that this method is fast and capable of generating circuits which are more economical than those generated by traditional design approaches. In addition, we take into account practical design considerations at high-frequency applications, where the component values are frequency-dependent and restricted to some discrete values. Experimental results show that our method can effectively generate not only compliant but also economical circuits for practical design tasks.

Many image and video compression algorithms work by splitting the image into blocks and producing variable-length code bits for each block data. If variable-length code data are transmitted consecutively over error-prone channel without any error protection technique, the receiving decoder cannot decode the stream properly. So the standard image and video compression algorithms insert some redundant information into the stream to provide some protection against channel errors. One of such redundancy is resynchronization marker, which enables the decoder to restart the decoding process from a known state in the event of transmission errors, but its frequent use should be restricted not to consume bandwidth too much. The Error Resilient Entropy Code (EREC) is well known method which can regain synchronization without any redundant information. It can work with the overall prefix codes, which many image compression methods use. This paper proposes an improvement to FEREC (Fast Error-Resilient Entropy Coding). It first calculates initial searching position according to bit lengths of consecutive blocks. Second, initial offset is decided using statistical distribution of long and short blocks, and initial offset is adjusted to insure all possible offset value can be examined. The proposed algorithm can speed up the construction of EREC slots, and can preserve compressed image quality in the event of transmission errors. The simulation result shows that the quality of transmitted image is enhanced about 0.3-3.5 dB compared with the existing FEREC when random channel error happens.

The efficiency of algorithms managing data caches has a major impact on the performance of systems that utilize client-side data caching. In these systems, two versions of data can be maintained without additional overhead by exploiting the replication of data in the server's buffer and clients' caches. In this paper, we present a new cache consistency algorithm employing versions: Two Versions-Callback Locking (2V-CBL). Our experimental results indicate that 2V-CBL provides good performance, and in particular outperforms a leading cache consistency algorithm, Asynchronous Avoidance-based Cache Consistency, when some clients run only read-only transactions.

We introduce a method, so called FC method, for maintaining software resources, such as source codes and design documents, in consumer electronics products. Because a consumer electronics product is frequently and rapidly revised, software components in such product are also revised in the same way. However, it is not so easy for software engineers to follow the revision of the product because requirements changes for the product, including the changes of its functionalities and its hardware components, are largely independent of the structure of current software resources. FC method lets software engineers to restructure software resources, especially design documents, stepwise so as to follow the requirements changes for the product easily. We report an application of this method in our company to validate it. From the application, we can confirm that the quality of software was improved about in twice, and that efficiency of development process was also improved over four times.

There have been many arguments that the underlying structure of natural languages is beyond the descriptive capacity of context-free languages. A well-known example is tree adjoining grammars; less common are spine grammars, linear indexed grammars, head grammars, and combinatory categorial grammars. It is known that these models of grammars have the same generative power of string languages and fall into the class of mildly context-sensitive grammars. For an automaton, it is known that the class of languages accepted by transfer pushdown automata is exactly the class of linear indexed languages. In this paper, deterministic transfer pushdown automata is introduced. We will show that the language accepted by a deterministic transfer pushdown automaton is generated by an unambiguous spine grammar. Moreover, we will show that there exists an inherently ambiguous language.

Mainly, a uniform linear array (ULA) has been used for DOA estimation of coherent signals because we can apply the spatial smoothing preprocessing (SSP) technique. However, estimation by a ULA has ambiguity due to the symmetry, and the estimation accuracy depends on the DOA. Although these problems can be solved by using a uniform circular array (UCA), we cannot estimate the DOA of coherent signals because the SSP technique cannot be applied directly to the UCA. In this paper, we propose to estimate 2-dimensional DOA (polar angles and azimuth angles) estimation of coherent signals using a cylindrical array which is composed of stacked UCAs.