This paper proposes a new maximal ratio combining (MRC) frequency diversity automatic-repeat-request (ARQ) scheme suitable for high-speed orthogonal frequency division multiplexing (OFDM) systems that is based on the conventional packet combining ARQ scheme. The proposed scheme regularly changes the previously prepared subcarrier assignment pattern at each retransmission according to the number of retransmissions. This scheme sharply reduces the number of ARQ retransmissions and much improves the throughput performance in slow fading environments by virtue of the frequency diversity effect while it requires no complex adaptive operations. Computer simulation results show that the proposed scheme reduces the required number of retransmissions to about 3 at the accumulative correct packet reception rate (ACPRR) of 0.9.

The design of a liner decorrelating detector for multi-processing gain code-division multiple-access (MPG-CDMA) systems is proposed, and its performance is discussed. As the result, the performance improvement by this detector is confirmed. Also, it is found that that the degrees of the noise enhancement depend on the processing gains of the signals.

This paper proposes a short delay, error-resilient video transmission scheme for mobile radio channels. Compressed video data are sensitive to channel error. Video coding schemes such as H. 263 use variable length coding so channel error can cause synchronization failure in the decoder and fatally degrade the reconstructed video sequence by triggering intra- and inter-frame error propagation. ARQ prevents all forms of error propagation but significantly increases the transmission delay of the video frame. We propose a new error control scheme to reduces the delay incurred by ARQ; the receiving buffer can transmits the video frame data to the video decoder even if not all ARQ frames containing the video frame are received. The encoder transmits additional information, the Macro Block (MB) size, in the video frame header. Upon receiving this information, the receiving buffer can determine MB length which allows MB de-synchronization to be prevented. For example, if an ARQ frame is lost, the decoder determines the position of the missing MB and replace this MB with the equivalent block in the previous video frame; this prevents intra-frame error propagation. When all ARQ frames are received and decoded correctly, the video frame in the reference video memory is replaced with the correctly decoded one. Simulation results show that the proposed scheme can minimize the delay and the reduction in frame rate caused by retransmission control without intra- and inter-error propagation.

This paper proposes a coherent detection scheme that can reduce the estimation errors of the carrier phase due to Gaussian noise in communication systems where pilot symbol assisted modulation is employed to compensate for Rician fading distortion. This paper introduces two functions in addition to conventional fading estimation methods using Wiener interpolation, etc. The first is the weighted average function for reducing the estimation errors of the fading distortion detected by pilot symbols. The second is the moving average function for estimating the phase errors that are residual after being compensated for by the estimated fading distortion. This paper evaluates the bit error rate (BER) performance for the proposed method in both Rician fading channel and additive white Gaussian noise (AWGN) channel by computer simulation. Simulation results verify that the BER performance of the proposed method is superior to that of a conventional method in both Rician fading channel and AWGN channel. Simulation results also confirm that the degradation of the BER performance of the proposed method is only 0.1 dB in AWGN channel and only 0.3 dB in Rician fading channel compared with the theoretical curves even if we reduce the number of computations by simplifying the calculation of interpolation coefficients optimized for Wiener interpolation.

Multimedia mobile communication systems are expected to be realized in the near future. In such systems, multipath fading can cause severe degradations of the quality of the communications due to its wide bandwidth, especially in urban areas. Adaptive array antennas can be attractive solution for overcoming the multipath fading. Suppression can be achieved with the adaptive array by cophasing and combining multipath signals in the space and time domain. On the other hand, the concept of software antenna has been proposed. The software antenna recognizes radiowave environments and appropriately reconfigures itself for the signal processing required by the recognized environment. Efficient implementations can be expected if these functions are realized by the software. In this paper, we propose two types of the adaptive array systems which is reconfigurable depending on the radiowave environment as a realization of the concept of the software antenna. They recognize the environment by using the eigenvalue decomposition of space domain correlation matrices and reconfigure their structures of the signal processing. The principle and performance are examined by theoretical means and through computer simulations.

Hallen's integral equation for cylindrical antennas is modified to deal with finite gap excitation. Because it is based on more realistic modeling, the solution is more accurate, and the convergence is guaranteed. The new equation is written with a new excitation function dependent on the gap width. The moment method analysis is presented where the piecewise sinusoidal surface current functions are used in Galerkin's procedure. Total, external and internal current distributions can be determined. Numerical results for cylindrical antennas with wide variety of gap width and radius are shown, and are compared with the numerical results by the Pocklington type integral equation and those by measurement.

In this paper, we propose a dynamic TDMA with priority-based request packet transmission scheme (D-TDMA/PRPTS) which applies priority-based request packet transmission scheme instead of slotted ALOHA (S-ALOHA). D-TDMA/PRPTS can avoid collisions between voice request packets and data request packets and transmit voice request packets preferentially. This makes D-TDMA/PRPTS enlarge the system capacity for voice users with SAD. We analyze voice packet dropping probability and channel utilization for voice traffic by using an appropriate Markov model. We also present simulation results to verify the analysis and to investigate data performances as well, with the voice-data integrated scenario.

We present a symbolic language emptiness check algorithm based on forward state traversal. A verification property is given by a set of error traces written in ω-regular expression and is manipulated explicitly as a non-deterministic state transition graph. State space of the design model is implicitly traversed along the explicit graph. This method has a large amount of flexibility for controlling state traversal on the property space. It should become a good framework of incremental or approximate verification of ω-regular properties.

In this paper we present a Quality of Service (QoS) management architecture for distributed multimedia applications in heterogeneous communication environments of wired and wireless networks. Gaps in network performance such as bandwidths and error rates between wired and wireless networks, as well as gaps in terminal performance in media handling between desktop computers and handheld computers, bring about heterogeneities. Furthermore, even performance gaps among various desktop computers cause heterogeneities. As a result of these heterogeneities in network and terminal performances and various user preferences, the QoS requirement from each receiver is different. Therefore, mechanisms that adjust and satisfy each QoS requirement are needed. We propose a proxy server called Communication Coordination Server (CCS), which intermediates a video server and a receiver and manages the QoS coordination. The CCS performs QoS admission, adjustment, and allocation mechanisms to satisfy the user's QoS requirement. Then transcoding is used to realize the allocated QoS, and it decodes the input video stream from the video server and encodes it within the CCS. A QoS mapping mechanism that translates application-level QoS into resource-level QoS is needed for the QoS admission. We also propose a new QoS mapping mechanism using spline functions that enables a continuous QoS translation. We have built a CCS prototype in our laboratory testbed, and have verified that the CCS can resolve the heterogeneities between the server and receiver by the QoS adjustment mechanism of the transcoding and the QoS admission.

In several design methods for Pass-transistor Logic (PTL) circuits, Boolean functions are expressed as OBDDs in decomposed form and then the component OBDDs are directly mapped to PTL cells. The total size of OBDDs (number of nodes) corresponds to the circuit size. In this paper, we investigate a method for PTL synthesis based on exact minimization of Free BDDs (FBDDs). FBDDs are well-studied extension of OBDDs with free variable ordering on each path. We present statistics showing that more than 56% of 616126 NPN-equivalence classes of 5-variable Boolean functions have minimum FBDDs with less size than their OBDDs. This result can be used for PTL synthesis as libraries. We also applied the exact minimization algorithm of FBDDs to the minimization of subcircuits in the synthesis for MCNC benchmarks and found up to 5% size reduction.

A parallel detailed router based on the area division is one of important tools to overcome the increase of CPU time required for routing of a very large multilayer SOG. In order to conduct routing in each divided area independently, fictitious terminals are introduced on the border of each divided area, and routes connected to the fictitious terminals are concatenated to complete the final detailed routes. In this paper, we consider a problem how to position such fictitious terminals on borders, so as to make each detailed routing in a divided area easy. We formulate this problem as a minimum cost assignment problem, and propose an iterative improvement algorithm. We also give some experimental results which indicate the effectiveness of the algorithm.

This paper proposes a hardware/software cosynthesis system for digital signal processor cores and a hardware/software partitioning algorithm which is one of the key issues for the system. The target processor has a VLIW-type core which can be composed of a processor kernel, multiple data memory buses (X-bus and Y-bus), hardware loop units, addressing units, and multiple functional units. The processor kernel includes five pipeline stages (RISC-type kernel) or three pipeline stages (DSP-type kernel). Given an application program written in the C language and a set of application data, the system synthesizes a processor core by selecting an appropriate kernel (RISC-type or DSP-type kernel) and required hardware units according to the application program/data and the hardware costs. The system also generates the object code for the application program and a software environment (compiler and simulator) for the processor core. The experimental results demonstrate that the system synthesizes processor cores effectively according to the features of an application program and the synthesized processor cores execute most application programs with the minimum number of clock cycles compared with several existing processors.

Newer off-chip DRAM families, including Synchronous DRAMs (SDRAMs) and RAMBUS DRAMs (RDRAMs), are becoming standard choices for the design of high-performance systems. Although previous work in High-Level Synthesis (HLS) has addressed exploiting features of page-mode DRAMs, techniques do not exist for exploiting the two key features of these newer DRAM families that boost memory performance and help overcome bandwidth limitations: (1) burst mode access, and (2) interleaved access through multiple banks. We address pre-synthesis optimizations on the input behavior that extract and exploit the burst mode and multiple bank interleaved access modes of these newer DRAM families, so that these features can be exploited fully during the HLS trajectory. Our experiments, run on a suite of memory-intensive benchmarks using a contemporary SDRAM library, demonstrate significant performance improvements of up to 62.5% over the naive approach, and improvements of up to 16.7% over the previous approach that considered only page-mode or extended-data-out (EDO) DRAMS.

The design of high performance-circuits using Field-Programmable Gate Arrays (FPGAs) requires a balance between the FPGA's architecture and CAD algorithms. Conventional FPGAs and CAD algorithms are developed independently, which makes it difficult to implement application circuits. To solve this problem, we developed a CAD-verified FPGA whose architecture was designed at the same time as the CAD algorithms. This paper shows how a CAD-verified FPGA architecture can simplify a routing algorithm. The algorithm is studied in terms of computational complexity and is simplified using the properties of our FPGA (switch module structure and the number of routing resources). The routing algorithm is almost one hundred times faster than that of the conventional router, and the quality of its circuits is also improved.

We investigated the reflection of light caused by sharp bends in optical fiber experimentally. The position distribution of reflection power was measured using an OTDR and an OLCR. We found that the reflection power increased linearly as the logarithm of the bending loss increased, which agrees with expectation from a simple theoretical model. We believe that the light we observed was part of the leaked light, which was reflected between the primary and secondary coatings.

Given a Petri net N=(P, T, E), a siphon is a set S of places such that the set of input transitions to S is included in the set of output transitions from S. Concerning extraction of one or more minimal siphons containing a given specified set Q of places, the paper shows several results on polynomial time solvability and NP-completeness, mainly for the case |Q| 1.

This paper describes the effectiveness of compact semiconductor optical amplifiers (SOAs) in the photonic transport system (PTS). Such amplifiers are small enough to permit high-density packaging. SOAs, having unsaturated signal gain of 10 dB and saturation output power of 10 dBm, can improve the Q-value by 3 over the SOA input power range of 10 dB. Within this range, the signal transport distance can be expanded from 360 km to 600 km by placing SOAs on individual optical channels in a PTS even though the amplified spontaneous emission (ASE) generated by individual SOAs is combined with the optical signals and delivered to the same output fiber. This result indicates that it is useful to employ compact SOAs in the PTS for enlarging the distances between nodes.

A new feature parameter based on a discrete wavelet transform is proposed for word boundary detection of isolated utterances. The sum of standard deviation of wavelet coefficients in the third coarse and weighted first detailed scale is defined as a new feature parameter for endpoint detection. Experimental results demonstrate the superiority of the proposed feature to the conventional ones in capturing word boundaries even in noisy speech.

Given a Petri net PN=(P, T, E), a siphon is a set S of places such that the set of input transitions to S is included in the set of output transitions from S. Concerning extraction of minimal siphons containing a given specified set Q of places, the paper proposes three algorithms based on branch-and-bound method for enumerating, if any, all minimal siphons containing Q, as well as for extracting such one minimal siphon.

RSPICE, a fast timing simulator for large digital MOS circuits, is presented in this paper. A new table-based region-wise linear MOS transistor model and the analytical solution of the generic sub-circuit primitive are applied to calculate the transient response of digital MOS circuits. The body effect of pass transistors is included in the MOS model and the floating capacitor network can be handled by this sub-circuit primitive as well. In RSPICE, MOS transistors with a DC path are grouped into a DC-connected block (DCCB), and DCCBs with a feedback path are combined as a strongly connected component (SCC). RSPICE orders SCCs by Tarjan's algorithm and simulates ordered SCCs one by one. DCCBs are basic cells in RSPICE and any DCCB can be mapped into one or more sub-circuit primitives. In order to calculate the transient response of these primitives analytically, RSPICE approximates the input signals of the primitive by piecewise linear functions. To compromise the simulation accuracy and run time, partial waveform and partial time convergent (PWPTC) combined with dynamic windowing technique is applied to simulate SCCs. Other key issues of RSPICE, such as circuit partition, pass-transistor and floating-capacitor processing, simulation-flow control and waveform modification are also discussed in detail. Compared with HSPICE , the simulation result of RSPICE is very accurate with an error less than 3%, but the speed is 1-2 orders over HSPICE.