A new hardware algorithm for the block matching video motion estimation is presented. The algorithm works in the full-search fashion but unlike the Full-Search Block Matching Algorithm (FSBMA) it adjusts the number of computations dynamically to variable picture contents. Due to incorporated mechanism of data-driven thresholding, the proposed algorithm performs as four times as less operations comparing to the FSBMA while maintaining the same quality of results. Its hardware implementation is simple and compact. A supportive hardware design as well as simulation results on benchmarks are outlined.

This paper proposes applications of a code-division multiplexing technique to VLSI systems free from interconnection problems. We employ a pseudo-random orthogonal m-sequence carrier as a multiplexable information carrier to achieve efficient data transmission. Using orthogonal property of m-sequences, we can multiplex several computational activities into a single circuit, and execute in parallel using multiplexed data transmission with reduced interconnection. Also, randomness of m-sequences offers the high tolerance to interference (jamming), and suppression of dynamic range of signals while maintaining a sufficient signal-to-noise ratio (SNR). We demonstrate application examples of multiplex computing circuits, neural networks, and spread-spectrum image processing to show the advantages.

A novel analog-computation system using quantum-dot spin glass is proposed. Analog computation is a processing method that solves a mathematical problem by applying an analogy of a physical system to the problem. A 2D array of quantum dots is constructed by mixing two-dot (antiferromagnetic interaction) and three-dot (ferromagnetic interaction) systems. The simulation results show that the array shows spin-glass-like behavior. We then mapped two combinatorial optimization problems onto the quantum-dot spin glasses, and found their optimal solutions. The results demonstrate that quantum-dot spin glass can perform analog computation and solve a complex mathematical problem.

A novel multiple-access optical network architecture is presented that not only employs the WDM technique but also divides networks. The subnetworks are connected to each other via a wavelength-dependent interconnection network, and pairs of subnetworks are optically linked with different combinations for each wavelength. Through an analysis of the throughput and delay for the slotted ALOHA protocol, the architecture is confirmed to be improved from the conventional one that employs only the WDM technique. For example, the improvement ratio of the throughput for a four-wavelength network is 2.4, and that for an eight-wavelength network is 4.4.

Shared multibuffer ATM switches are attractive since they can extend memory bandwidth by the use of multiple independent buffer memories. Although the parallel accessibility allows a considerable improvement in memory bandwidth, a proper assignment of memory addresses to cells is necessary to better utilize the potential bandwidth. In this paper, we present an efficient cell placement strategy for shared multibuffer ATM switches. It is based on a combination of two key concepts, uniform distribution for writes and reference locality for reads. The former is to reduce cell loss ratio due to overflow and write-access conflicts. The latter is to have cells destined for the same output port read from the same buffer memory to minimize read-access conflicts. A single threshold is employed to assign memory locations adaptively depending on the cell distribution among the shared buffer memories. The proposed strategy is shown to outperform the existing ones, in terms of cell loss ratio, cell delay, and throughput. Moreover, the performance gains have been made with a simple control circuit.

We developd a method of implementing a multiple-valued Hopfield network on electronic circuits by using single-electron circuit technology. The single-electron circuit shows quantized behavior in its operation because of the discrete tunnel transport of electrons. It can therefore be successfully used for implementing neuron operation of the multiple-valued Hopfield network. The authors developed a single-electron neuron circuit that can produce the staircase transfer function required for the multiple-valued neuron. A method for constructing a multiple-valued Hopfield network by combining the neuron circuits was also developed. A sample network was designed that solves an example of the quadratic integer-programming problem. And a computer simulation demonstrated that the sample network can converge to its optimal state that represents the correct solution to the problem.

This paper gives a detailed presentation of a "vision chip" for a very fast detection of motion vectors. The chip's design consists of a parallel pixel array and column parallel block-matching processors. Each pixel of the pixel array contains a photo detector, an edge detector and 4 bits of memory. In the detection of motion vectors, first, the gray level image is binarized by the edge detector and subsequently the binary edge data is used in the block matching processor. The block-matching takes place locally in pixel and globally in column. The chip can create a dense field of motion where a vector is assigned to each pixel by overlapping 2 2 target blocks. A prototype with 16 16 pixels and four block-matching processors has been designed and implemented. Preliminary results obtained by the prototype are shown.

This letter proposes an integrated approach to multimedia ATM network design. An optimization model that combines the physical layer design with the logical layer design is developed. A key feature of the model is that the objective to be maximized is a profit function. It includes more comprehensive cost functions for the physical and logical layers. A simple heuristic algorithm to solve the model is presented. It should be useful in practice for network designers and operators. Some numerical examples are given to illustrate the application of the model and the algorithm.

A partial buffer sharing scheme is proposed as loss-priority control for a finite buffer with batch Poisson inputs under a whole batch acceptance rule. Customer and batch loss probabilities for high- and low-priority customers are derived under this batch acceptance rule using a supplementary variable method. A comparison of the partial buffer sharing scheme and a system without loss-priority control is made in terms of admissible offered load. Whole batch acceptance and partial batch acceptance rules are also compared in terms of admissible offered load.

A typical user is concerned only with the quality of service of a network on an end-to-end basis. Therefore, how end-to-end requirements are mapped into the local switching node requirements and maximum network utilization is a function of network internal design. In this paper, we address the problem of QOS allocation. We derived an optimal QOS allocation policy and decided the maximum utilization bound in a deterministic traffic model. We adopted the worst case delay bound as the end-to-end and local QOS requirement. With (σ, ρ) traffic model, we derived a formula for delay bound and the number of connections. We found that with the delay bound as the QOS metric, there is a significant difference in the performance of allocation policies. We also developed an evaluation strategy to analyze allocation policies. The numerical results for two simple network topologies: tandem network model and uneven traffic load model, compare the equal allocation policy with the optimal allocation policy and show the correctness and efficiency of QOS allocation policy.

This paper proposes a novel universal line termination scheme for the ONUs (optical network units) of fiber-optic local access systems. Its main feature is that only low cost AD/DA converters for Hi-Fi audio are needed. Because audio AD/DA converters are insufficient for ISDN basic rate access (● 320kbaud) and cause waveform distortion, we develop a simple detection algorithm that does not use any equalizing filter. The algorithm can handle plural channels with one general purpose MPU (micro-processing unit). Based on this, a novel architecture for a fiber-optic local access system is presented that removes the MPUs from each optical network unit (ONU) and places them in the central office (CO). The proposed system yields a small, service-uniform ONU that supports a wide range of narrow-band services (POTS & ISDN) with no distinction. To realize this system at the lowest possible cost, a high-speed code division multiplexing (CDM) scheme with novel code word sets is developed.

An analog vector quantization processor has been designed based on the neuron-MOS (νMOS) technology. In order to achieve a high integrating density, template information is merged into the matching cell (the absolute value circuitry) using the νMOS ROM technology. A new-architecture νMOS winner-take-all (WTA) circuit is employed for fully-parallel search for the minimum-distance vector. The WTA performs multi-resolution winner search with an automatic feedback gain control. A test chip having 256 16-element fixed template vectors has been built in a 1.5-µm double-polysilicon CMOS technology with the chip size of 7.2 mm 7.2 mm, and the basic operation of the circuits has been demonstrated.

In this paper we propose a heterogeneous agents model that represents speculative dynamics by using the synergetic approach. We consider the markets for three securities (a stock, a bond, and a foreign currency). Each market consists of two typical types of investors: fundamentalists and bandwagon traders. We show the characteristic patterns of speculative prices (speculative bubbles and speculative chaos) which are generated by trading between the fundamentalists and bandwagon traders.

A new logic-in-memory VLSI architecture based on multiple-valued floating-gate-MOS pass-transistor logic is proposed to solve the communication bottleneck between memory and logic modules. Multiple-valued stored data are represented by the threshold voltage of a floating-gate MOS transistor, so that a single floating-gate MOS transistor is effectively employed to merge multiple-valued threshold-literal and pass-switch functions. As an application, a four-valued logic-in-memory VLSI for high-speed pattern recognition is also presented. The proposed VLSI detects a stored reference word with the minimum Manhattan distance between a 16-bit input word and 16-bit stored reference words. The effective chip area, the switching delay and the power dissipation of a new four-valued full adder, which is a key component of the proposed logic-in-memory VLSI, are reduced to about 33 percent, 67 percent and 24 percent, respectively, in comparison with those of the corresponding binary CMOS implementation under a 0.5-µm flash EEPROM technology.

The current-voltage characteristics of a single electron transistor (SET) in the resonant transport mode are investigated. In the future when SET devices are applied to integrated electronics, the quantum effect will seriously modify their characteristics in ultra-small geometry. The current will be dominated by the resonant transport through narrow energy levels in the dot. The simple case of a two-level system is analyzed and the transport mechanism is clarified. The transport property at low temperatures (higher than the Kondo temperature) in the low tunneling rate limit is discussed, and a current map where current values are classified in the gate bias-drain bias plane is provided. It was shown that the dynamic aspect of electron flow seriously influences the current value.

This paper presents the generator polynomial matrices and the upper bound on the constraint length of punctured convolutional codes (PCCs), respectively. By virtue of these properties, we provide the puncturing realizations of the good known nonsystematic and systematic high rate CCs.

A new vector-matching circuit technology has been developed aiming at compact implementation of maximum likelihood search engine for neuron-MOS associative processor. The new matching cell developed in this work possessed the template information in the form of an analog mask ROM and calculates the absolute value of difference between the template vector and the input vector components. The analog-mask ROM merged matching cell is composed of only five transistors to be compared with our earlier-version memory separated matching cell of 13 transistors. In addition, the undesirable cell-to-cell data interference through the common floating node ("boot-strap effect") has been eliminated without using power-consuming current source loads in source followers. As a result, dc-current-free matching cell operation has been established, making it possible to build a low-power, high-density search engine. Test circuits were fabricated by a 0.8-µm double-polysilicon double-metal n-well CMOS process, and the circuit operation has been experimentally verified.

Adaptive channel estimation filters are presented for coherent DS-CDMA reverse link using time-multiplexed pilot and parallel pilot structures. Fast transmit power control (TPC) is adopted in the reverse link. Fading statistical properties are not preserved when fast TPC is used. When fading is slow, the channel is similar to non-fading channel, but its starts to vary as fading become faster since fast TPC cannot track fading perfectly. A pragmatic approach is used in this paper to derive adaptive channel estimation filter. The filter coefficients are updated based on the measured autocorrelation function of the instantaneous channel estimate. The bit error rate (BER) performance under frequency selective Rayleigh fading is evaluated by computer simulation to show that the adaptive channel estimation filter provides superior performance to the previously proposed non-adaptive WMSA filter.

This paper proposes non-volatile analog memory circuits using pulse-width modulation (PWM) methods. The conventional analog memory using floating gate device has a trade-off between programming speed and precision because of the constant width of write pulses. The proposed circuits attain high programming speed with high precision by using PWM write pulses. Three circuits are proposed and their performance is evaluated using SPICE simulation. The simulation results show that fast programming time less than 20 µs, high updating resolution of 11 bits, and high precision more than 7 bits are achieved.

When we have a singular Cab curve with many rational points, we had better to construct linear codes on its normalization rather than the original curve. The only obstacle to construct linear codes on the normalization is finding a basis of L( Q) having pairwise distinct pole orders at Q, where Q is the unique place of the Cab curve at infinity. We present an algorithm finding such a basis from defining equations of the normalization of the original Cab curve.