In general, when many functions and services are added to a system, verification and validation become difficult. In design and development in telecommunication services, conflicts that arise from combined telecommunication services have been discussed from various viewpoints. However, correctly and efficiently detecting all conflicts is still not possible and the resolution of conflicts primarily depends on expert designers, who are finding that these problems are beyond their ability. Thus, the burden on the designer must also be alleviated at the design stage. Service interference, which is discussed in this paper, is a kind of conflict. A problem of service interference is that during service, other services interfere with the ongoing service behavior. That is to say, a strange state arises, or an input event doesn't work, or a strange transition occurs, etc. The detection of service interference by only comparing states among services is not enough since the state transition must be considered in the service interference. This paper proposes how to automatically detect the service interference with a rule-based system and an extended adjacency matrix. The proposed method uses and combines features of both the adjacency matrix and rule-based system. The method first generates the extended adjacency matrix by the rule application, then extracts sequences of the state, the event, and the rule applications, and then detects the service interference with the extracted sequences.

A neuron MOS transistor has a floating gate and multiple input gates which are capacitively coupling with the floating gate. Dramatic reduction in the number of transistors and interconnections was achieved by employing the neuron MOS in circuit designs. Since the neuron MOS gate electrode is electrically floating, it is not necessarily easy to calculate the floating gate potential using circuit simulator SPICE. In order to simulate floating gate neuron MOS circuits, a macromodel which calculates the floating gate potential combining resistances and dependent voltage and current sources has been proposed. Eight kinds of neuron MOS circuits were designed and fabricated by a double polysilicon two level metal 1.2 µ m CMOS process. Utilizing SPICE, all the neuron MOS circuits were confirmed to operate correctly. The apparent threshold voltage as seen from the input gate in the 2-input n-channel neuron MOS transistor is arbitrarily changed by a control gate signal. Multi-input neuron MOS inverters and neuron MOS full adder circuits have been successfully simulated. Moreover, the effectiveness of the proposed macromodel has been experimentally verified by fabricated circuit measurements. Measured results confirmed that 3-input neuron MOS inverter outputs the low level when the number of input gates to which a high level is applied is more than half of all input gates.

The complexity of designing communication protocols has lead researchers to develop various techniques for designing and verifying protocols. One of the most important techniques is a compositional technique. Using a compositional technique, a large and complex protocol is designed and verified by composing small and simple protocols which are easy to handle, design and verify. Unlike the other compositional approaches, we propose compositional techniques for simultaneously composing service specifications and protocol specifications based on Formal Description Techniques (FDTs) called LOTOS. The proposed techniques consider alternative, sequential, interrupt and parallel composition of service specifications and protocol specifications. The composite service specification and the composite protocol specification preserve the original behaviour and the correctness properties of individual service specifications and protocol specifications. We use the weak bisimulation equivalence (), to represent the correctness properties between the service specification and the protocol specification. When a protocol specification is weak bisimulation equivalent to a service specification, the protocol satisfies all the logical properties of a communication protocol as well as provides the services that are specified in the service specification.

A selectively grown Si1-xGex base heterojunction bipolar transistor (HBT) was fabricated, and effects of Ge and B profiles on the device performance were investigated. Since no obvious leakage current was observed, it is shown that good crystallinity of Si1-xGex was achieved by using a UHV/CVD system with high-pressure H2 pre-cleaning of the substrate. Very high current gain of 29,000 was obtained in an HBT with a uniform Ge profile by both increasing electron injection from the emitter to the base and reducing band gap energy in the base. Since the Early voltage is affected by the grading of Ge content in the base, the HBT with the graded Ge profile provides very high Early voltage. However, the breakdown voltage is degraded by increasing Ge content because of reducing bandgap energy and changing dopant profile. To increase the cutoff frequency, dopant diffusion must be suppressed, and carrier acceleration by the internal drift field with the graded Ge profile has an additional effect. By doing them, an extremely high cutoff frequency of 130 GHz was obtained in HBT with graded Ge profiles.

At the Information-technology Promotion Agency (IPA), we have been developing a network intrusion detection system called IDA (Intrusion Detection Agent system). IDA system has two distinctive features that most conventional intrusion detection systems lack. First, it has a mechanism for tracing the origin of a break-in by means of mobile agents. Second, it has a new and efficient method of detecting intrusions: rather than continuously monitoring the user's activities, it watches for an event that meets the criteria of an MLSI (Mark Left by Suspected Intruders) and may relate to an intrusion. By this method, IDA described herein can reduce the processing overhead of systems and networks. At present, IDA can detect local attacks that are initiated against a machine to which the attacker already has access and he or she attempts to exceed his or her authority. This paper mainly describes how IDA detects local attacks and traces intrusions.

In a real-time system, it is required to reduce the response time to an interrupt signal, as well as the execution time of a Real-Time Operating System (RTOS). In order to satisfy this requirement, we have proposed a method of implementing some of the functionalities of an RTOS using hardware. Based on this idea, we have implemented a VLSI chip, called STRON (silicon TRON: The Realtime Operating system Nucleus), to enhance the performance of an RTOS, where the STRON chip works as a peripheral unit of any MPU. In this paper we describe the hardware architecture of the STRON chip and the performance evaluation results of the RTOS using the STRON chip. The following results were obtained. (1) The STRON chip is implemented in only about 10,000 gates when the number of each object (task, event flag, semaphore, and interrupt) is 7. (2) The task scheduler can execute within 8 clocks in a fixed period using the hardware algorithm when the number of tasks is 7. (3) Most of the basic µITRON system calls using the STRON chip can be executed in a fixed period of a few microseconds. (4) The execution time of a system call, measured by a multitask application program model, can be reduced to about one-fifth that in the case of the conventional software RTOS. (5) The total performance, including context switching, is about 2.2 times faster than that of the software RTOS. We conclude that the execution time of the part of the system call implemented by the STRON chip can almost be ignored, but the part of the interface software and context switching related to the architecture of a MPU strongly influence the total performance of an RTOS.

A semi-synchronous circuit is a circuit in which every register is ticked by a clock periodically, but not necessarily simultaneously. In a semi-synchronous circuit, the minimum delay between registers may be critical with respect to the clock period of the circuit, while it does not affect the clock period of an ordinary synchronous circuit. In this paper, we discuss a delay insertion method which makes such a semi-synchronous circuit faster. The maximum delay-to-register ratio over the cycles in the circuit gives a lower bound of the clock period. We show that this bound is achieved in the semi-synchronous framework by the proposing gate-level delay insertion method.

This paper presents a novel implication-based method for logic minimization in large-scale, multi-level networks. It significantly reduces network size through repeated addition and removal of redundant subnetworks, utilizing multi-signal implications and relationships among these implications. These are handled on a transitive implication graph, proposed in this paper, which offers the practical use of implications for logic minimization. The proposed method holds great promise for the achievement of an interactive logic design environment for large-scale networks.

In this paper, we present a traffic scheduling algorithm, called the Delay-Bound Monotonic with Average Rate Reservation (DM/ARR), which generates minimum output burstiness streams. We assume that connection i is policed by the leaky bucket algorithm with parameters (σi,ρi) where σi is the bucket size (or burstiness) and ρi is the leaky rate. Compared with the totally isolated scheme where connection i is allocated a bandwidth ri=max{σi/di,ρi} (di is the delay bound requirement of connection i), the DM/ARR algorithm has a better performance in the sense that it has a larger admission region. We prove that, among all possible scheduling algorithms that satisfy the delay bound requirements of established connections, DM/ARR results in the minimum output burstiness. This is important because a smaller burstiness implies a smoother traffic and thus the receiver (or next switch node in a multihop network) can handle it more easily. Numerical results show that the admission region of the DM/ARR algorithm is close to that of the earliest deadline first algorithm. A packetized version is studied for ATM networks.

Weighted summation (W-SUM) operation of multi-input signals plays an important role in signal processing, image compression and communication systems. Conventional digital LSI implementation for the massive high-speed W-SUM operations usually consumes a lot of power, and the power dissipation linearly increases with the operational frequencies. Analog or digital-analog mixed technology may provide a solution to this problem, but the large scale integration for analog circuits especially for digital-analog mixed circuits faces some difficulties in terms of circuit design, mixed-simulation, physical layout and anti-noises. To practically integrate large scale analog or digital-analog mixed circuits, the simplicity of the analog circuits are usually required. In this paper, we present a solution to realize the parallel W-SUM operations of multi-input analog signals based on our developed digital-controlled analog operational circuits. The major features of the proposed circuits include the simplicity in the circuitry architecture and the advantage in the dissipation power, which make it easy to be designed and to be integrated in large scale. To improve the design efficiency, a Top-Down design approach for mixed LSI implementation is proposed. The proposed W-SUM circuits and the Top-Down design approach have been practically used in the LSI implementation for a series of programmable finite impulse response (FIR) filters and matched filters applied in adaptive signal processing and the mobile communication systems based on the wideband code division multiple access (W-CDMA) technology.

This paper proposes an ASIP performance optimization method taking clock frequency into account. The performance of an instruction set processor can be measured using the execution time of an application program, which can be determined by the clock cycles to perform the application program divided by the applied clock frequency. Therefore, the clock frequency should also be tuned in order to maximize the performance of the processor under the given design constraints. Experimental results show that the proposed method determines an optimal combination of FUs considering clock frequency.

This paper describes an IC implementation of current-mode chaotic neuron circuit for the chaotic neural network. The chaotic neuron circuit which composes of a first generation switched-current integrator and a conventional current amplifier is fabricated in a standard 0.8 µ m CMOS technology. Experimental results of the chaotic neuron circuit reproduce the dynamical behavior of the chaotic neuron model.

There are two approaches for formal verification of sequential designs or finite state machines: language containment checking and symbolic model checking. To verify designs of practical size, in these two approaches, designs are represented symbolically, in practice, by ordered binary decision diagrams. In the conventional algorithm for language containment checking, finite automata given as specifications are also represented symbolically. This paper proposes a new method, called partially explicit method for checking language containment. By representing states of finite automata given as specifications explicitly, this method can remove redundant computations, and as a result, provide better performance than the conventional method which uses the product machines of designs and specifications. The experimental results show that this approach is effective in checking language containment symbolically.

In this paper, we introduce a high-speed and low-power Phase-Frequency Detector (PFD) that is designed using a modified TSPC (True Single-Phase Clock) positive edge triggered D flip-flop . The proposed PFD has a simple structure with using only 19 transistors. The operation range of this PFD is over 1.4 GHz without using additional prescaler circuits. Furthermore, the PFD has a dead zone less than 0.01ns in the phase characteristics and has low phase sensitivity errors. The phase and frequency error detection range is not limited as in the case of the pt-type and nc-type PFDs. Also, the PFD is independent of the duty cycle of input signals. Also, a new charge-pump circuit is presented that is based on a charge-amplifier. A stand-by current of the proposed charge-pump circuit enhances the speed of charge-pump and removes the charge sharing which causes a phase noise in the charge pump PLL. Furthermore, the effect of clock feedthrough is reduced by separating the output stage from up and down signal. The simulation results base on a third order PLL are presented to verify the lock in process with the proposed PFD and charge pump circuits. The proposed PFD and charge-pump circuits are designed using 0.8 µm CMOS technology with 5 V supply voltage.

In this study, wave propagation phenomena of phase states are observed at van der Pol oscillators coupled by inductors as a ladder. For the case of 17 oscillators, interesting wave propagation phenomena of phase states are found. By using the relationship between phase states and oscillation frequencies, the mechanisms of the propagation and the reflection of wave are explained. Circuit experimental results agree well with computer calculated results qualitatively.

This paper deals with two-processor scheduling for a class of program nets, that are acyclic and SWITCH-less, and of which each node has unity node firing time. Firstly, we introduce a hybrid priority list L* that generates optimal schedules for the nets whose AND-nodes possess at most single input edge. Then we extend L* to suit for general program nets to give a new priority list L**. Finally, we use genetic algorithm to do the performance evaluation for the schedules generated by L** and show these schedules are quite close to optimal ones.

The paper argues that a radical shift in the market for communications services is emerging, driven by the mass availability of cheap bandwidth, computing and global mobility combined with the pervasive rise of Internet based data services. At the same time, the Operation Support Systems (OSS's*) that are essential in order to create business value from these technologies are lagging behind market need. The authors argue for a re-think of the humble management system into a complete software wrap-around of the network to deliver a value creation platform - as different from yesterday's OSS as the bakelite telephone is from today's tri-band mobile handsets. This software will be based on product standards, not paper ones and will require a major shift of gears from the position of today. This value creation platform will be built from advanced, component based software delivered through a very different market model to that of today. Much of this technology exists; we simply need critical mass behind a common approach. The discussion in this paper represents the personal views of the authors and does not necessarily represent the views of any organisation.

RSPICE, a fast timing simulator for large digital MOS circuits, is presented in this paper. A new table-based region-wise linear MOS transistor model and the analytical solution of the generic sub-circuit primitive are applied to calculate the transient response of digital MOS circuits. The body effect of pass transistors is included in the MOS model and the floating capacitor network can be handled by this sub-circuit primitive as well. In RSPICE, MOS transistors with a DC path are grouped into a DC-connected block (DCCB), and DCCBs with a feedback path are combined as a strongly connected component (SCC). RSPICE orders SCCs by Tarjan's algorithm and simulates ordered SCCs one by one. DCCBs are basic cells in RSPICE and any DCCB can be mapped into one or more sub-circuit primitives. In order to calculate the transient response of these primitives analytically, RSPICE approximates the input signals of the primitive by piecewise linear functions. To compromise the simulation accuracy and run time, partial waveform and partial time convergent (PWPTC) combined with dynamic windowing technique is applied to simulate SCCs. Other key issues of RSPICE, such as circuit partition, pass-transistor and floating-capacitor processing, simulation-flow control and waveform modification are also discussed in detail. Compared with HSPICE , the simulation result of RSPICE is very accurate with an error less than 3%, but the speed is 1-2 orders over HSPICE.

Millimeter-wave systems increasingly are entering into commercial systems, both for communication and sensors for traffic or industrial applications. In many cases, circuit technology of the involved front-ends includes monolithic and hybrid integrated circuits and even waveguide components like filters or antenna feeds. In addition to the standard technical and environmental requirements, these front-ends have to be fabricated in large quantities at very low cost. After a short review of the problems and some general interconnect and packaging techniques for mm-wave front-ends, achievements of a research program will be presented at the example of components for a 28 GHz communication front-end. Emphasis is put on a novel feed-through structure using multilayer carrier substrates for mm-wave circuits, some advances in electromagnetic field coupling for interconnects to mm-wave MMICs, and the realization of packages including waveguide components by plastic injection molding and electroplating. Results of filters and a diplexer produced in this way are shown, including pretuning of the filters to compensate the shrinking of the plastic parts during cooling.

A novel multipath diversity scheme used in TDD-CDMA systems is presented. A FIR filter is added in the transmitter, while a RAKE combiner is used in the receiver. The optimum FIR filter problem may be viewed as an eigenvalue problem. The multiple antennas system is also analyzed. Results show that this new scheme can greatly improve the output Signal to Noise Ratio (SNR) compared with conventional RAKE receiver or Pre-RAKE diversity system.