A GSM900/DCS1800 dual-band AlGaAs/GaAs HBT (heterojunction bipolar transistor) MMIC (monolithic microwave integrated circuit) power amplifier has been developed. It includes power amplifiers for GSM900 and DCS1800, constant voltage bias circuits and a d. c. switch. In order to achieve high efficiency, the outside-base/center-via-hole layout is applied to the final-stage HBT of the MMIC amplifier. The layout can realize uniform output load impedance and thermal distribution of each HBT finger. The developed MMIC amplifier could provided output power of 34.5 dBm and power-added efficiency of 53.4% for GSM900, and output power of 32.0 dBm and power-added efficiency of 41.8% for DCS1800.

Silicon-based monolithic microwave integrated circuits (MMICs) present an interesting option for low-cost consumer wireless systems. SiGe/Si heterojunction bipolar transistors (HBTs) are a major driving force behind Si-based MMICs, because they offer excellent microwave performance without aggressive lateral scaling. This article reviews opportunities for receiver frontend components (low-noise amplifiers and mixers) using SiGe HBTs.

Internet communication is increasingly becoming an important element in daily life. Keeping this network safe from malicious elements is an urgent task for network management. To maintain the security level networks are generally, monitored for indications of usage with ill-intentions. Such indications are events which need to be collated, correlated and analyzed in real-time to be effective. However, on an average medium to large size network the number of such events are very large. This makes it practically impossible to analyze the information in real-time and provide the necessary security measures. In this paper, we propose a mechanism that keeps the number of events, to be analyzed, low thereby making it possible to provide ample security measures. We discuss a real-time Intrusion Detection System (IDS) for detecting network attacks. The system looks out for TCP ACK/RST packets, which are generally caused by network scans. The system can extract the tendency of network flows in real-time, based on the newly developed time-based clustering and Dynamic Access Tree creation techniques. The algorithm, implemented and deployed on a medium size backbone network using RMON (Remote MONitoring) technology, successfully detected 195 intrusion attempts during a one month period. The results of the pilot deployment are discussed. In this paper, the proposal, implementation and evaluation will be described.

This letter is concerned with a new algorithm which can be used to design a time-domain equalizer (TEQ) for xDSL systems employing the discrete multitone (DMT) modulation. The proposed algorithm, derived by neglecting the terms which do not affect the performance of a DMT system in ARMA modeling, is shown to have a good performance compared with the previous TEQ algorithms even with a significantly lower computational complexity. In addition, the proposed algorithm does not require the channel impulse response or training sequence, since all processing is made only with the received data.

A procedure for radar target discrimination is presented in this paper. The scheme includes an enhancement of late-time noisy scattering data based on a proposed signal processing algorithm and a decision procedure using previously known resonance annihilation filters. The signal processing stage is specifically adapted to scattering signals and makes use of the results of the singularity expansion method. It is based on a signal reconstruction using the SVD of a data matrix with a suitable choice of the number of singular vectors employed. To justify the inclusion of this stage, this procedure is shown to maintain the signal characteristics necessary to identify the scattered response. Simulation results clearly reveal a significant improvement due to the inclusion of the proposed stage. This improvement becomes especially important when the noise level is high or the targets to be discriminated (five regular polygonal loops) have a similar geometry.

In this paper, a method of Transmission Power Control (TPC) for Orthogonal Frequency Division Multiplexing Direct Sequence Code Division Multiple Access (OFDM-DS-CDMA), in order to compensate for power attenuation at each subcarrier, is proposed. Instead of assigning same power levels for all-subcarriers, different transmission power levels are assigned to different subcarriers, according to the attenuation of the subcarriers. System performance, in terms of Bit Error Rate (BER), has been evaluated by Monte Carlo simulation. The simulation results presented significant improvement, the proposed system performed much better than the system without TPC. It is shown that the Each Carrier TPC performs better than All Carriers TPC, which all carriers are controlled uniformly, hence Each Carrier TPC is more suitable for OFDM-DS-CDMA system.

The Matrix-Pencil (MP) method is applied to the estimation of the undesired radiation from the microstrip line discontinuities. The Q factors are obtained from the complex resonant frequencies estimated from FDTD transient field by using MP. The number of the damped oscillations is estimated by using MDL which is widely used as an information theoretic criterion for the model order estimation.

In general, when many functions and services are added to a system, verification and validation become difficult. In design and development in telecommunication services, conflicts that arise from combined telecommunication services have been discussed from various viewpoints. However, correctly and efficiently detecting all conflicts is still not possible and the resolution of conflicts primarily depends on expert designers, who are finding that these problems are beyond their ability. Thus, the burden on the designer must also be alleviated at the design stage. Service interference, which is discussed in this paper, is a kind of conflict. A problem of service interference is that during service, other services interfere with the ongoing service behavior. That is to say, a strange state arises, or an input event doesn't work, or a strange transition occurs, etc. The detection of service interference by only comparing states among services is not enough since the state transition must be considered in the service interference. This paper proposes how to automatically detect the service interference with a rule-based system and an extended adjacency matrix. The proposed method uses and combines features of both the adjacency matrix and rule-based system. The method first generates the extended adjacency matrix by the rule application, then extracts sequences of the state, the event, and the rule applications, and then detects the service interference with the extracted sequences.

In this paper we present a Quality of Service (QoS) management architecture for distributed multimedia applications in heterogeneous communication environments of wired and wireless networks. Gaps in network performance such as bandwidths and error rates between wired and wireless networks, as well as gaps in terminal performance in media handling between desktop computers and handheld computers, bring about heterogeneities. Furthermore, even performance gaps among various desktop computers cause heterogeneities. As a result of these heterogeneities in network and terminal performances and various user preferences, the QoS requirement from each receiver is different. Therefore, mechanisms that adjust and satisfy each QoS requirement are needed. We propose a proxy server called Communication Coordination Server (CCS), which intermediates a video server and a receiver and manages the QoS coordination. The CCS performs QoS admission, adjustment, and allocation mechanisms to satisfy the user's QoS requirement. Then transcoding is used to realize the allocated QoS, and it decodes the input video stream from the video server and encodes it within the CCS. A QoS mapping mechanism that translates application-level QoS into resource-level QoS is needed for the QoS admission. We also propose a new QoS mapping mechanism using spline functions that enables a continuous QoS translation. We have built a CCS prototype in our laboratory testbed, and have verified that the CCS can resolve the heterogeneities between the server and receiver by the QoS adjustment mechanism of the transcoding and the QoS admission.

A MMIC power amplifier operating with a single-supply (3.0 V) has been developed for 5.8 GHz Japanese Electronic Toll Collection (ETC) System. The present MMIC contains two FETs, matching circuits (input, intermediate and output matching circuits), and two drain bias circuits. High dielectric constant material SrTiO3 (STO) is used for by-pass and input coupling capacitors. Very small die size of 0.77 mm2 has been realized by using the STO capacitors and negative feedback circuit technology. High 1 dB output gain compression point (P1dB) of 13 dBm, high gain of 21.4 dB and low dissipation current of 41.3 mA have been achieved under 3.0 V single-supply condition.

A. Chatterjee et al. proposed tests with linearity property for gate delay faults to determine, at a required clock speed, whether a circuit under test is a marginal chip or not. The latest transition time at the primary output is changed linearly with the size of the gate delay fault when the proposed test is applied to the circuit under test. To authors' knowledge, no reports on an algorithmic method for generating tests with linearity property have been presented before. In this paper, we propose a method for generating tests with linearity property for gate delay faults. The proposed method introduces a new extended timed calculus to calculate the size of a given gate delay fault that can be propagated to the primary output. The method has been applied to ISCAS benchmark circuits under the unit delay model.

We present a symbolic language emptiness check algorithm based on forward state traversal. A verification property is given by a set of error traces written in ω-regular expression and is manipulated explicitly as a non-deterministic state transition graph. State space of the design model is implicitly traversed along the explicit graph. This method has a large amount of flexibility for controlling state traversal on the property space. It should become a good framework of incremental or approximate verification of ω-regular properties.

This paper proposes an ASIP performance optimization method taking clock frequency into account. The performance of an instruction set processor can be measured using the execution time of an application program, which can be determined by the clock cycles to perform the application program divided by the applied clock frequency. Therefore, the clock frequency should also be tuned in order to maximize the performance of the processor under the given design constraints. Experimental results show that the proposed method determines an optimal combination of FUs considering clock frequency.

In several design methods for Pass-transistor Logic (PTL) circuits, Boolean functions are expressed as OBDDs in decomposed form and then the component OBDDs are directly mapped to PTL cells. The total size of OBDDs (number of nodes) corresponds to the circuit size. In this paper, we investigate a method for PTL synthesis based on exact minimization of Free BDDs (FBDDs). FBDDs are well-studied extension of OBDDs with free variable ordering on each path. We present statistics showing that more than 56% of 616126 NPN-equivalence classes of 5-variable Boolean functions have minimum FBDDs with less size than their OBDDs. This result can be used for PTL synthesis as libraries. We also applied the exact minimization algorithm of FBDDs to the minimization of subcircuits in the synthesis for MCNC benchmarks and found up to 5% size reduction.

In this paper, we present a traffic scheduling algorithm, called the Delay-Bound Monotonic with Average Rate Reservation (DM/ARR), which generates minimum output burstiness streams. We assume that connection i is policed by the leaky bucket algorithm with parameters (σi,ρi) where σi is the bucket size (or burstiness) and ρi is the leaky rate. Compared with the totally isolated scheme where connection i is allocated a bandwidth ri=max{σi/di,ρi} (di is the delay bound requirement of connection i), the DM/ARR algorithm has a better performance in the sense that it has a larger admission region. We prove that, among all possible scheduling algorithms that satisfy the delay bound requirements of established connections, DM/ARR results in the minimum output burstiness. This is important because a smaller burstiness implies a smoother traffic and thus the receiver (or next switch node in a multihop network) can handle it more easily. Numerical results show that the admission region of the DM/ARR algorithm is close to that of the earliest deadline first algorithm. A packetized version is studied for ATM networks.

A selectively grown Si1-xGex base heterojunction bipolar transistor (HBT) was fabricated, and effects of Ge and B profiles on the device performance were investigated. Since no obvious leakage current was observed, it is shown that good crystallinity of Si1-xGex was achieved by using a UHV/CVD system with high-pressure H2 pre-cleaning of the substrate. Very high current gain of 29,000 was obtained in an HBT with a uniform Ge profile by both increasing electron injection from the emitter to the base and reducing band gap energy in the base. Since the Early voltage is affected by the grading of Ge content in the base, the HBT with the graded Ge profile provides very high Early voltage. However, the breakdown voltage is degraded by increasing Ge content because of reducing bandgap energy and changing dopant profile. To increase the cutoff frequency, dopant diffusion must be suppressed, and carrier acceleration by the internal drift field with the graded Ge profile has an additional effect. By doing them, an extremely high cutoff frequency of 130 GHz was obtained in HBT with graded Ge profiles.

A method to recognize planar objects undergoing affine transformation is proposed in this paper. The method is based upon wavelet multiscale features and Hopfield neural networks. The feature vector consists of the multiscale wavelet transformed extremal evolution. The evolution contains the information of the contour primitives in a multiscale manner, which can be used to discriminate dominant points, hence a good initial state of the Hopfield network can be obtained. Such good initiation enables the network to converge more efficiently. A wavelet normalization scheme was applied to make our method scale invariant and to reduce the distortion resulting from normalizing the object contours. The Hopfield neural network was employed as a global processing mechanism for feature matching and made our method suitable to recognize planar objects whose shape distortion arising from an affine transformation. The Hopfield network was improved to guarantee unique and more stable matching results. A new matching evaluation scheme, which is computationally efficient, was proposed to evaluate the goodness of matching. Two sets of images, noiseless and noisy industrial tools, undergoing affine transformation were used to test the performance of the proposed method. Experimental results showed that our method is not only effective and robust under affine transformation but also can limit the effect of noises.

An emitter coupled logic (ECL) compatible low-power GaAs 8:1 multiplexer (MUX) and 1:8 demultiplexer (DEMUX) for 10-Gb/s optical communication systems has been developed. In order to decrease the power consumption and to maximize the timing margin, we estimated the power consumption for direct-coupled FET logic (DCFL) and source-coupled FET logic (SCFL) circuits in terms of the D-type flip-flop (D-FF) operating speed and the duty-ratio variation. Based on the result, we used SCFL circuits in the clock-generating circuit and the circuits operating at 10 Gb/s, and we used DCFL circuits in the circuits operating below 5 Gb/s. These ICs, which are mounted on ceramic packages, operate at up to 10 Gb/s with power consumption of 1.2 W for the 8:1 MUX and 1.0 W for the 1:8 DEMUX. This is the lowest power consumption yet reported for 10-Gb/s 8:1 MUX and 1:8 DEMUX.

Given a Petri net N=(P, T, E), a siphon is a set S of places such that the set of input transitions to S is included in the set of output transitions from S. Concerning extraction of one or more minimal siphons containing a given specified set Q of places, the paper shows several results on polynomial time solvability and NP-completeness, mainly for the case |Q| 1.

Newer off-chip DRAM families, including Synchronous DRAMs (SDRAMs) and RAMBUS DRAMs (RDRAMs), are becoming standard choices for the design of high-performance systems. Although previous work in High-Level Synthesis (HLS) has addressed exploiting features of page-mode DRAMs, techniques do not exist for exploiting the two key features of these newer DRAM families that boost memory performance and help overcome bandwidth limitations: (1) burst mode access, and (2) interleaved access through multiple banks. We address pre-synthesis optimizations on the input behavior that extract and exploit the burst mode and multiple bank interleaved access modes of these newer DRAM families, so that these features can be exploited fully during the HLS trajectory. Our experiments, run on a suite of memory-intensive benchmarks using a contemporary SDRAM library, demonstrate significant performance improvements of up to 62.5% over the naive approach, and improvements of up to 16.7% over the previous approach that considered only page-mode or extended-data-out (EDO) DRAMS.