To one double-breaker model, experimental investigation on blow open force was carried out. It demonstrates that the ratio between the emerging blow open force and arc power FB/ui decreases with the arcing time, the contact gap has less effect on FB/ui, and the characteristics of the blow open force are similar when the peak value of the short circuit current is beyond 4 kA. Then, according to the experimental data and conclusions, considering the influence of blow open force, the interruption process of molded case circuit breakers (MCCBs) was investigated. It demonstrates the blow open force has significant influence on interruption process and the proposed method is effective to evaluate new design of MCCBs.

Among the broadband wireless communication standards utilized to satisfy the demand for multimedia services, time division duplexing (TDD) is satisfactory for the asymmetric data transmission emphasized in Internet services. In this system, the transition between receiving a frame and transmitting a response must be bounded for an effective use of radio resources. However, the minimized inter-frame space-time requires high processing power. The aim of the present paper is to gain insight into the time latency at the turn-around time of a TDD operation. We also propose a simplified new processor, which is a terminal device-friendly architecture that includes prediction and preparation to support processing of burst-type traffic.

A 32-bit embedded RISC microcontroller core targeted for automotive, industrial, and PC-peripheral applications has been developed to offer the smaller code size, lower-latency instruction and interrupt processing needed for next-generation microcontrollers. The 360 MIPS/400MFLOPS/200 MHz core--based on the Harvard bus architecture--uses 0.13/0.15-µm CMOS technology and consists of a CPU, FPU, and register banks. To reduce the size of the control programs, new instructions have been added to the instruction set. These new instructions, as well as an enhanced C compiler, produce object files about 25% smaller than those for a previous designed core. A dual-issue superscalar structure consisting of three- or five-stage pipelines provides instruction processing with low latency. The cycle performance is thus an average of 1.8 times faster than the previous designed core. The superscalar structure is used to save 19 CPU registers in parallel when executing interrupt processing. That is, it saves the 19 CPU registers to the resister bank by accessing four registers at a time. This structure significantly improves interrupt response time from 37 cycles to 6 cycles.

An efficient and simple approach to consonant/vowel (C/V) segmentation by incorporating the SNR improvement of a speech enhancement system with the energy variation of two adjacent frames is proposed. Experimental results show that the proposed scheme performs well in segmenting C/V for a spontaneously spoken utterance.

This paper deals with the use of neural network rule extraction techniques based on the Genetic Programming (GP) to build intelligent and explanatory evaluation systems. Recent development in algorithms that extract rules from trained neural networks enable us to generate classification rules in spite of their intrinsically black-box nature. However, in the original decompositional method looking at the internal structure of the networks, the comprehensive methods combining the output to the inputs using parameters are complicated. Then, in our paper, we utilized the GP to automatize the rule extraction process in the trained neural networks where the statements changed into a binary classification. Even though the production (classification) rule generation based on the GP alone are applicable straightforward to the underlying problems for decision making, but in the original GP method production rules include many statements described by arithmetic expressions as well as basic logical expressions, and it makes the rule generation process very complicated. Therefore, we utilize the neural network and binary classification to obtain simple and relevant classification rules in real applications by avoiding straightforward applications of the GP procedure to the arithmetic expressions. At first, the pruning process of weight among neurons is applied to obtain simple but substantial binary expressions which are used as statements is classification rules. Then, the GP is applied to generate ultimate rules. As applications, we generate rules to prediction of bankruptcy and creditworthiness for binary classifications, and the apply the method to multi-level classification of corporate bonds (rating) by using the financial indicators.

To overcome the mobility impact on RSVP, many schemes have been proposed based on Mobile IP regional registration and passive reservation in advance. Although the regional registration and in advance reservation reduce the QoS interruption time, the latter may demand intolerable bandwidth. This letter introduces a novel approach to reduce the QoS interruption time by maximizing the localization of QoS re-establishment in the regional registration environment. The proposed scheme identifies the exact path segment affected by mobility. The QoS interruption time of the proposed scheme is comparable to its low bound without in advance reservation.

Nonlinear distortions in an anti-series varactor pair (ASVP) are analyzed by a perturbation method. To the authors' knowledge, this paper presents the first derivation of an analytical expression that explicitly shows intermodulation and harmonic distortions of the ASVP. In addition to canceling the expected even-order distortion, the third-order distortion can be suppressed simultaneously when a certain condition is satisfied. We also find that the second- and third-order distortions can be greatly suppressed without dependence on dc bias voltage if the varactors in the ASVP have an ideal abrupt p-n junction. These theoretical predictions are verified by measuring the second- and third-order harmonic distortions of an ASVP. The experimental results show that the second-order harmonic distortion is suppressed by approximately 20 dB. The third-order harmonic distortion is suppressed to the same extent in the theoretically predicted dc bias voltage range.

This paper proposes an independent control for parallel-connected multiple uninterruptible power supply (UPS) systems based upon a very simple control scheme. Here, the amplitude and phase angle of the output voltage are the controllable variables. With the only measurement of the output current, the active and reactive components are calculated to define the control variables. The entire system including the equations for the circuit, control and voltage limiters is well represented by a small-signal model, in which the computation of its eigenvalues constitutes the stability proof of the system. The root locus diagram gives an overall panorama of the system performance as a function of a certain gain and it aims to aid the further understanding and the design of the control. The experimental verification is carried out using a mere proportional-integral control scheme, which is a special case of the general control equation used in the theoretical analysis. For some situations, experiments show a flow of lateral current between UPS's, which causes an unbalanced current distribution. By increasing the proportional gain of the control equation for the output voltage amplitude, the lateral current can be substantially suppressed with a consequent improvement of the load sharing. Experimental results under various conditions show excellent results in terms of synchronization, load sharing and stability for three distinct output rating UPS's connected in parallel.

In order to get the knowledge of gas dynamics in interruption process of molded case circuit breakers, a quenching chamber model with gas-driven arc is proposed. The two-dimensional optical fiber digital testing system has been used to measure the arc current, arc voltage, pressure in the quenching chamber, and the movement of the arc when interrupting the 10 kA prospective current in different conditions. The influence of venting conditions, the configuration of splitter plates and gassing material characteristics on the performance of gas-driven arc has investigated. It demonstrates that the performance can be improved effectively by the ways of closing the bottom venting, adopting shorter splitter plate configuration, and POM and Nylon gassing materials.

A timer-based scheme is proposed to manage information within terminal and service profiles for both incall registration/deregistration of UPT users and incall registration resets of terminal owners. In the timer-based scheme, information related to incall registration for a UPT user in a terminal profile is deleted due to a timer expiration without accessing the terminal profile. The performance of the timer-based scheme is compared with the previously proposed request-based scheme in terms of; 1) total cost and, 2) the number of terminal profile accesses per unit time for a terminal. Even though provision of the timer-based scheme requires the modification of incoming call delivery procedure, the timer-based scheme can reduce both the total cost and the number of terminal profile accesses compared to the previously proposed request-based scheme.

Superscalar processors can achieve increased performance by issuing instructions Out-of-Order (OoO) from the original instruction stream. Implementing an OoO instruction scheme requires a hardware mechanism to prevent incorrectly executed instructions from updating registers values. In addition, performance decreases if data dependencies, a branch or a trap among instructions appears. To this end we propose a new mechanism named Dynamic Fast Issue (DFI) mechanism to issue instructions in an OoO fashion to multiple parallel functional units without considerable hardware complexity. The above system, which will be implemented in our Superscalar Functional Assignments Register Microprocessor(FARM), solves data dependencies, supports precise interrupt and branch prediction, which are the main problems associated with the dynamic scheduling of instructions in superscalar machines. Results are written only once,Write-once, directly into the register file (RF). To ensure that results are written in order in their appropriate output registers, a record of instruction order and state is maintained by a status buffer (STB). A 64 entries integrated register file is implemented to hold both renamed and logical registers. To recover the processor state from an interrupt or a branch miss-prediction, a status buffer (STB) and a recovery list table (RLT) are implemented. Novel aspects of the above system architecture as well as the principle underlying this process and the constraints that must be met is presented. Performance evaluation results are performed through full-pipelined-level architectural simulator and SPECint95 benchmark programs.

The complexity of designing communication protocols has lead researchers to develop various techniques for designing and verifying protocols. One of the most important techniques is a compositional technique. Using a compositional technique, a large and complex protocol is designed and verified by composing small and simple protocols which are easy to handle, design and verify. Unlike the other compositional approaches, we propose compositional techniques for simultaneously composing service specifications and protocol specifications based on Formal Description Techniques (FDTs) called LOTOS. The proposed techniques consider alternative, sequential, interrupt and parallel composition of service specifications and protocol specifications. The composite service specification and the composite protocol specification preserve the original behaviour and the correctness properties of individual service specifications and protocol specifications. We use the weak bisimulation equivalence (), to represent the correctness properties between the service specification and the protocol specification. When a protocol specification is weak bisimulation equivalent to a service specification, the protocol satisfies all the logical properties of a communication protocol as well as provides the services that are specified in the service specification.

In universal personal telecommunication (UPT) environments, UPT networks retain information related to incall/outcall registration in UPT user service profiles in order to provide incoming UPT calls for UPT users in any location who have registered at a terminal. As UPT networks support incall registration, terminal users can be different from terminal owners, and several UPT users can register for incoming calls on a single terminal. Therefore, appropriate third-party protection procedures are needed to protect the rights of terminal owners. A terminal profile database can be used to store information regarding terminal states and incall UPT users registered on a terminal in order to enable third-party protection procedures. In order to manage information within both the terminal profile and the service profile, we propose a request-based scheme for incall registration/deregistration of UPT users and incall registration resets of terminal owners. We evaluate the performance of the scheme in terms of; 1) total cost and, 2) the number of terminal profile accesses per unit time for a terminal.

This paper presents a new approach to the precise interrupt handling problem in modern processors with multiple out-of-order issues. It is difficult to implement a precise interrupt scheme in the processors because later instructions may change the process states before their preceding instructions have completed. We propose a fast precise interrupt handling scheme which can recover the precise state in one cycle if an interrupt occurs. In addition, the scheme removes all the associative searching operations which are inevitable in the previous approaches. To deal with the renaming of destination registers, we present a new bank-based register file which is indexed by bank index tables containing the bank identifiers of renamed register entries. Simulation results based on the superscalar MIPS architecture show that the register file with 3 banks is a good trade-off between high performance and low complexity.

Multimedia communications often require intramedia synchronization for video data to prevent potential playout discontinuity while still retaining satisfactory playout throughput. In this paper, we propose a novel intra-video synchronization mechanism, called the Video Smoother, particularly suitable for low-end multimedia applications, such as video conferencing. Generally, the Video Smoother dynamically adopts various playout rates according to the number of frames in the playout buffer in an attempt to compensate for the delay jitter introduced from networks. In essence, if the number of frames in the buffer exceeds a given threshold (TH), the Smoother employs a maximum playout rate. Otherwise, the Smoother employs linearly or exponentially reduced rates to eliminate playout pauses resulting from the emptiness of the playout buffer. To determine optimal THs achieving a minimum of playout discontinuity and a maximum of playout throughput under various bursty traffic, we propose an analytic model assuming incoming traffic following an Interrupted Bernoulli arrival Process (IBP). As a result, optimal THs can be analytically determined resulting in superior playout quality under various arrivals and loads of networks. Finally, we display simulation results which demonstrate that, compared to the playout without intra-video synchronization (instant playout), the Video Smoother achieves superior smooth playout and compatible throughput.

Asynchronous Transfer Mode (ATM) networks are expected to support a diverse mix of traffic sources requiring different Quality Of Service (QOS) guarantees. This paper initially examines several existing scheduling disciplines which offer delay guarantees in ATM switches. Among them, the Earliest-Due-Date (EDD) discipline has been regarded as one of the most promising scheduling disciplines. The EDD discipline schedules the departure of a cell belonging to a call based on the delay priority assigned for that call during the call set-up. Supporting n delay-based service classes through the use of n respective urgency numbers D0 to Dn-1 (D0D1 Dn-1), EDD allows a class-i cell to precede any class-j (j>i) cell arriving not prior to (Dj-Di)-slot time. The main goal of the paper is to determine the urgency numbers (Dis), based on an in-depth queueing analysis, in an attempt to offer ninety-nine percentile delay guarantees for higher priority calls under various traffic loads. In the analysis, we derive system-time distributions for both high- and low-priority cells based on a discrete-time, single-server queueing model assuming renewal and non-renewal arrival processes. The validity of the analysis is justified via simulation. With the urgency numbers (Dis) determined, we further propose a feasible efficient VLSI implementation architecture for the EDD scheduling discipline, furnishing the realization of QOS guarantees in ATM switches.

This paper discusses crystal-growth and device-design issues associated with the development of high-performance InP/InGaAs heretostructure bipolar transistors (HBTs). It is shown that a highly Si-doped n+-subcollector in the HBT structure causes anomalous Zn redistribution during metalorganic vapor phase epitaxial (MOVPE) growth. A thermodynamical model of and a useful solution to this big problem are presented. A novel hybrid structure consisting of an abrupt emitter-base heterojunction and a compositionally-graded base is shown to enhance nonequilibrium base transport and thereby increase current gain and cutoff frequency fT. A double-heterostructure bipolar transistor (DHBT) with a step-graded InGaAsP collector can improve collector breakdown behavior without any speed penalty. We also elucidate the effect of emitter size shrinkage on high-frequency performance. Maximum oscillation frequency fmax in excess of 250 GHz is reported.

The advance of mobile network and radio techniques has been rapidly expanding the service area for mobile terminals. Thus, mobile communications have been devoted to the improvement of terminal mobility (TM). Recently, the personal mobility (PM) concept appeared which gives a freedom to use personal telecommunication numbers at any terminal. Therefore, mobile network must next enable a user to access telecommunication services with his/her personal telecommunication number from any terminal at any geographic location. In other words, the mobile network must implement universal mobility (UM) that integrates TM and PM. This paper first provides a definition of UM. Next, it describes the identity and number configurations for UM and then presents network techniques for UM, i.e., the network architecture and UM management procedures. It also presents the current status of standardization on UM in the Personal Digital Cellular system (PDC) and Future Public Land Mobile Telecommunication Systems (FPLMTS).

Development of a large-scale mobile communications network (IMN: Intelligent Mobile communications Network), as an infrastructure integrating multimedia functions, is indispensable for the support of future mobile communication services aiming toward "personalization," "intelligence," and "multimedia services." This paper discusses the aims of mobile communications and the outline of network technology aspects of PDC (Personal Digital Cellular) network which is currently in service. In addition, the future prospect of mobile communication technologies is discussed with special focuses on the support of universal mobility, network architecture including mobile communications platform, and multimedia technologies in the transport and access systems.

The intelligent network services will considerably increase the amount of Control and OAM (Operation, Administration and Maintenance) Information (Ic&o) which will be stored in a huge number of distributed databases. Therefore, the management and the organization of databases have become critical issues for securing network performance. This paper studies one of the IN applications that is likely to be an important user of the Ic&o network, namely the Universal Personal Telecommunication (UPT). UPT enables the personal mobility, based on a UPT number related to the user and not a terminal equipment. The Ic&o information of UPT is carried through an ATM based transport network. Taking two fundamental parameters into consideration, namely delay time and the number of users, and two kinds of data location probabilities, this paper studies two basic procedures for finding target data in UPT databases, i.e., chaining and broadcasting. Results show that, when the data location probability is uniform, the broad-casting mode is the faster mode but, on the other hand, the chaining mode allows a larger number of users because the disk access time is less restrictive than in the broadcasting mode. Moreover, this study shows that increasing the number of databases also increases the allowed number of users up to a specific threshold. With a Broadcast Chaining mode, a better compromise between the delay time and the number of allowed users is obtained. If the probability depends on the location of databases (the probability is conversely proportional to the square of the number of searched databases), the results show that the chaining mode is preferable from both the number of users allowed and the delay time viewpoints. Finally, the implementation aspect is discussed.