Conventional Nyquist folding receiver (NYFR) uses zero crossing rising (ZCR) voltage times to control the RF sample clock, which is easily affected by noise. Moreover, the analog and digital parts are not synchronized so that the initial phase of the input signal is lost. Furthermore, it is assumed in most literature that the input signal is in a single Nyquist zone (NZ), which is inconsistent with the actual situation. In this paper, we propose an improved architecture denominated as a dual-channel NYFR with adjustable local oscillator (LOS) and an information recovery algorithm. The simulation results demonstrate the validity and viability of the proposed architecture and the corresponding algorithm.

This paper describes a simple-yet-effective control method for a DC-DC buck converter with voltage mode control (VMC), with a triangular wave generator (TWG) which regulates the slope of triangular wave based on the input and output voltages of the converter. Using the proposed TWG, both the load and line transient responses are improved. Since the TWG provides a line feed-forward control for the line transient response, it increases the open-loop bandwidth, and then better dynamic performance is obtained. Additional required circuit components are only a voltage controlled linear resistor (VCR) and a voltage controlled current source (VCCS). Compared with the conventional voltage control, the proposed method significantly improves the line and load transient responses. Furthermore this triangular wave slope regulation scheme is simple compared to digital feed-forward control scheme that requires non-linear calculation. Simulation results shows the effectiveness of the proposed method.

This paper presents an efficient algorithm for reporting all intersections among n given segments in the plane using work space of arbitrarily given size. More exactly, given a parameter s which is between Ω(1) and O(n) specifying the size of work space, the algorithm reports all the segment intersections in roughly O(n2/+ K) time using O(s) words of O(log n) bits, where K is the total number of intersecting pairs. The time complexity can be improved to O((n2/s) log s + K) when input segments have only some number of different slopes.

Face detection has been an independent technology playing an important role in more and more fields, which makes it necessary and urgent to have its architecture reconfigurable to meet different demands on detection capabilities. This paper proposed a face detection architecture, which could be adjusted by the user according to the background, the sensor resolution, the detection accuracy and speed in different situations. This user adjustable mode makes the reconfiguration simple and efficient, and is especially suitable for portable mobile terminals whose working condition often changes frequently. In addition, this architecture could work as an accelerator to constitute a larger and more powerful system integrated with other functional modules. Experimental results show that the reconfiguration of the architecture is very reasonable in face detection and synthesized report also indicates its advantage on little consumption of area and power.

This paper describes a new technique for the design of 3-terminal regulators in which the output voltage level can be adjusted without additional terminals or extra off-chip components. This circuit restricts the increase in the number of terminal pins by using a pin as both a voltage supply output and a voltage setup input. The voltage setup information is introduced using a serial control signal from outside the chip. Using the intermediate voltage level between the supply voltage and the regulator output, the adjustment data in the internal nonvolatile memory are safely updated without noise disturbance. To input the setup information into the chip in a stable manner, we developed a new 1-wire serial interface which combines key pattern matching and burst signal detection. To ensure high reliability, we suggested a quantitative method for evaluating the influence of noise in our new interface using a simple model with superimposed random noise. Circuits additional to those for a conventional 3-terminal regulator, include a 1-wire serial communication circuit, a low-capacity non-volatile memory, and a digital to analog (D/A) converter. A test chip was developed using 0.35 µm standard CMOS process, and there was almost no overhead to the conventional 3-terminal regulator in both chip area and power dissipation. In an on-board test with the test chip, we confirmed successful output voltage adjustment from 1.0 V to 2.7 V with approximately 6.5 mV precision.

Traditional algorithms for dynamic OFDMA resource allocation have relatively deterministic system capacity and user fairness. Thus, in this letter, an efficient scheme is proposed to flexibly adjust quality-of-service for users, which is achieved by appropriately setting minimum data-rate of each user.

Multiple Input Multiple Output (MIMO) represents a highly promising technique for 4G communication networks as it uses multiple antennas at the transmitter and receiver to improve the reliability of transmissions and to provide a high data rate. This paper introduces an adjustable scheduling algorithm for multi-user MIMO systems that can provide an advantageous trade-off solution between throughput maximization and fair resource allocation among users. Specifically, our algorithm is proposed as a solution to system requirement issues through the flexible control of fairness factors.

A scheme for a low-voltage CMOS syllabic-companding log domain filter with wide dynamic range is proposed and its prototype is presented. A nodal voltage which is fixed in a conventional filter based on the dynamically adjustable biasing (DAB) technique is adapted for change of input envelope to achieve wide dynamic range. Externally linear and time invariant (ELTI) relation between an input and an output is guaranteed by a state variable correction (SVC) circuit which is also proposed for low-voltage operation. To demonstrate the proposed scheme, a fifth-order Chebychev low-pass filter with 100-kHz cutoff frequency is designed and fabricated in a standard 0.35-µm CMOS process. The filter has a 78-dB dynamic range and consumes 200-µW power from a 0.8-V power supply.

In this paper, we presented a beam adjustable antenna made up of a slit waveguide and a dielectric slab. In order to change the radiation main-beam angle, we changed the phase constant of the waveguide mode by inserting a dielectric slab for perturbing its field distribution. The direction of radiation main-beam can be steered by dynamically changing the position of the dielectric slab. For the theoretical analysis, the dispersion relation, including the phase and attenuation constants, was determined by solving the transverse resonance equation. An agreement between the theoretical and experimental radiation pattern verifies the beam-steering mechanism. Up to 23beam-steering angle can be achieved using this approach.

We report tunable optical devices based on fiber Bragg gratings (FBGs), whose filtering characteristics are controlled by strain distributions. These devices include a widely wavelength tunable filter, a tunable group-velocity dispersion (GVD) compensator, a tunable dispersion slope (DS) compensator, and a variable-bandwidth optical add/drop multiplexer (OADM), which will play important roles for next-generation reconfigurable optical networks.

This paper describes an adaptive fingerprint-sensing scheme for a user authentication system with a fingerprint sensor LSI to obtain high-quality fingerprint images suitable for identification. The scheme is based on novel evaluation indexes of fingerprint-image quality and adjustable analog-to-digital (A/D) conversion. The scheme adjusts dynamically an A/D conversion range of the fingerprint sensor LSI while evaluating the image quality during real-time fingerprint-sensing operation. The evaluation indexes pertain to the contrast and the ridgelines of a fingerprint image. The A/D conversion range is adjusted by changing quantization resolution and offset. We developed a fingerprint sensor LSI and a user authentication system to evaluate the adaptive fingerprint-sensing scheme. The scheme obtained a fingerprint image suitable for identification and the system achieved an accurate identification rate with 0.36% of the false rejection rate (FRR) at 0.075% of the false acceptance rate (FAR). This confirms that the scheme is very effective in achieving accurate identification.

This paper describes a new special purpose Variable Gain Amplifier (VGA) using 0.5µm digital CMOS process. The new architecture allows the gain to be varied more than 20dB, and does not trade bandwidth for gain. Despite low power consumption (22mW) from a 3.3 Volt supply, the circuit has 310MHz -3dB bandwidth and shows low THD (-45dB) over its full frequency range. The new VGA architecture does not use any capacitor or resistor array for gain adjustment, thus it is very compact (0.14mm 0.26mm) and requires less power than conventional designs.