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[Keyword] algorithm(2137hit)

601-620hit(2137hit)

  • Dynamic Spectrum Allocation Based on MEG Algorithm

    Guangen WU  Pinyi REN  Zhou SU  

     
    PAPER-Wireless Communication Technologies

      Vol:
    E94-B No:11
      Page(s):
    3077-3088

    Dynamic spectrum allocation (DSA) based on secondary spectrum market is considered a promising technology to improve spectrum utilization efficiency and to relieve the wireless spectrum shortage problem. We propose a dynamic spectrum allocation algorithm named market equilibrium and game (MEG), and construct a complete secondary spectrum market. The market based on the MEG algorithm consists of two submarkets: multiple primary services providers (PSPs) and a dynamic spectrum allocation server (DSAS) form the high submarket, while the low submarket is composed of the DSAS and a number of secondary users. In the low submarket, the MEG algorithm provides a game type selection strategy. By this strategy, the DSAS can win more payoffs with lower unit spectrum price, which encourages secondary users to use more spectrum. A secondary user can also choose its preferable game type between dynamic game and Nash bargaining flexibly. On the other hand, a bargaining procedure in the high submarket is designed in the MEG algorithm to ensure that market equilibrium is quickly reached. A performance analysis shows that the strategy of game type selection is fair and feasible for both the DSAS and the secondary users. Moreover, the bargaining procedure is better than the existing algorithm which adjusts price step by step in the high submarket. Simulation results also demonstrate that the market fluctuation in the low submarket is passed to the high submarket by way of the DSAS. The MEG algorithm can effectively satisfy the highly-fluctuating demands from the secondary users. In addition, the MEG algorithm can improve the payoffs of all players and increase spectrum utilization efficiency.

  • High-Speed and Low-Complexity Decoding Architecture for Double Binary Turbo Code

    Kon-Woo KWON  Kwang-Hyun BAEK  Jeong Woo LEE  

     
    LETTER-VLSI Design Technology and CAD

      Vol:
    E94-A No:11
      Page(s):
    2458-2461

    We propose a high-speed and low-complexity architecture for the very large-scale integration (VLSI) implementation of the maximum a posteriori probability (MAP) algorithm suited to the double binary turbo decoder. For this purpose, equation manipulations on the conventional Linear-Log-MAP algorithm and architectural optimization are proposed. It is shown by synthesized simulations that the proposed architecture improves speed, area and power compared with the state-of-the-art Linear-Log-MAP architecture. It is also observed that the proposed architecture shows good overall performance in terms of error correction capability as well as decoder hardware's speed, complexity and throughput.

  • A Fast Systematic Optimized Comparison Algorithm for CNU Design of LDPC Decoders

    Jui-Hui HUNG  Sau-Gee CHEN  

     
    PAPER-Communication Theory and Signals

      Vol:
    E94-A No:11
      Page(s):
    2246-2253

    This work first investigates two existing check node unit (CNU) architectures for LDPC decoding: self-message-excluded CNU (SME-CNU) and two-minimum CNU (TM-CNU) architectures, and analyzes their area and timing complexities based on various realization approaches. Compared to TM-CNU architecture, SME-CNU architecture is faster in speed but with much higher complexity for comparison operations. To overcome this problem, this work proposes a novel systematic optimization algorithm for comparison operations required by SME-CNU architectures. The algorithm can automatically synthesize an optimized fast comparison operation that guarantees a shortest comparison delay time and a minimized total number of 2-input comparators. High speed is achieved by adopting parallel divide-and-conquer comparison operations, while the required comparators are minimized by developing a novel set construction algorithm that maximizes shareable comparison operations. As a result, the proposed design significantly reduces the required number of comparison operations, compared to conventional SME-CNU architectures, under the condition that both designs have the same speed performance. Besides, our preliminary hardware simulations show that the proposed design has comparable hardware complexity to low-complexity TM-CNU architectures.

  • Fast Shape Matching Using Statistical Features of Shape Contexts

    Moon-Jai LIM  Chan-Hee HAN  Si-Woong LEE  Yun-Ho KO  

     
    LETTER-Image Recognition, Computer Vision

      Vol:
    E94-D No:10
      Page(s):
    2056-2058

    A novel fast algorithm for shape matching using statistical features of shape contexts is presented. By pruning the candidate shapes using the moment-based statistical features of shape contexts, the required number of matching processes is dramatically reduced with negligible performance degradation. Experimental results demonstrate that the proposed algorithm reduces the pruning time up to 1/(r·n) compared with the conventional RSC algorithm while maintaining a similar or better performance, where n is the number of sampled points of a shape and r is the number of randomly selected representative shape contexts for the query shape.

  • Simplified Capacity-Based User Scheduling Algorithm for Multiuser MIMO Systems with Block Diagonalization Open Access

    Yuyuan CHANG  Kiyomichi ARAKI  

     
    PAPER-Wireless Communication Technologies

      Vol:
    E94-B No:10
      Page(s):
    2837-2846

    In multiple-input multiple-output (MIMO) systems, the multiuser MIMO (MU-MIMO) systems have the potential to provide higher channel capacity owing to multiuser and spatial diversity. Block diagonalization (BD) is one of the techniques to realize MU-MIMO systems, where multiuser interference can be completely cancelled and therefore several users can be supported simultaneously. When the number of multiantenna users is larger than the number of simultaneously receiving users, it is necessary to select the users that maximize the system capacity. However, computation complexity becomes prohibitive, especially when the number of multiantenna users is large. Thus simplified user scheduling algorithms are necessary for reducing the complexity of computation. This paper proposes a simplified capacity-based user scheduling algorithm, based on analysis of the capacity-based user selection criterion. We find a new criterion that is simplified by using the properties of Gram-Schmidt orthogonalization (GSO). In simulation results, the proposed algorithm provides higher sum rate capacity than the conventional simplified norm-based algorithm; and when signal-to-noise power ratio (SNR) is high, it provides performance similar to that of the conventional simplified capacity-based algorithm, which still requires high complexity. Fairness of the users is also taken into account. With the proportionally fair (PF) criterion, the proposed algorithm provides better performance (sum rate capacity or fairness of the users) than the conventional algorithms. Simulation results also shows that the proposed algorithm has lower complexity of computation than the conventional algorithms.

  • Acceleration of Flexible GMRES Using Fast Multipole Method for Implementation Based on Combined Tangential Formulation

    Hidetoshi CHIBA  Toru FUKASAWA  Hiroaki MIYASHITA  Yoshihiko KONISHI  

     
    PAPER-Electromagnetic Theory

      Vol:
    E94-C No:10
      Page(s):
    1661-1668

    In this study, we demonstrate an acceleration of flexible generalized minimal residual algorithm (FGMRES) implemented with the method of moments and the fast multipole method (FMM), based on a combined tangential formulation. For the implementation of the FGMRES incorporated with the FMM concept, we propose a new definition of the truncation number for the FMM operator within the inner solver. The proposed truncation number provides an optimal variable preconditioner by controlling the accuracy and computational cost of the inner iteration. Moreover, to further accelerate the convergence, we introduce the concept of a multistage preconditioner. Numerical experiments reveal that our new version of FGMRES, based on the proposed truncation number for the inner solver and the multistage preconditioner, achieves outstanding acceleration of the convergence for large-scale and practical electromagnetic scattering and radiation problems with several levels of geometrical complexity.

  • A New Calibration Algorithm Using Reference Materials for the Waveguide-Penetration Method

    Alfred KIK  Atsuhiro NISHIKATA  

     
    PAPER-Electromagnetic Compatibility(EMC)

      Vol:
    E94-B No:9
      Page(s):
    2549-2557

    The waveguide-penetration method is a method to measure the electrical properties of materials. In this method, a cylindrical object pierces a rectangular waveguide through a pair of holes at the centre of its broad walls. Then, the complex permittivity and permeability of the object are estimated from measured S-parameters after TRL calibration. This paper proposes a new calibration algorithm for the waveguide-penetration method. Reference materials with known electrical properties are fabricated in cylindrical shapes to fit into the holes in the waveguide and are used as calibration standards. The algorithm is formulated using the property of equal traces in similar matrices, and we show that at least two reference materials are needed to calibrate the system. The proposed algorithm yields a simpler means of calibration compared to TRL and is verified using measurements in the S-band. Also, the error sensitivity coefficients are derived. These coefficients give valuable information for the selection of reference materials.

  • Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems

    Takeshi KUMAKI  Tetsushi KOIDE  Hans Jurgen MATTAUSCH  Masaharu TAGAMI  Masakatsu ISHIZAKI  

     
    PAPER-Fundamentals of Information Systems

      Vol:
    E94-D No:9
      Page(s):
    1742-1754

    This paper presents a software-based parallel cryptographic solution with a massive-parallel memory-embedded SIMD matrix (MTX) for data-storage systems. MTX can have up to 2,048 2-bit processing elements, which are connected by a flexible switching network, and supports 2-bit 2,048-way bit-serial and word-parallel operations with a single command. Furthermore, a next-generation SIMD matrix called MX-2 has been developed by expanding processing-element capability of MTX from 2-bit to 4-bit processing. These SIMD matrix architectures are verified to be a better alternative for processing repeated-arithmetic and logical-operations in multimedia applications with low power consumption. Moreover, we have proposed combining Content Addressable Memory (CAM) technology with the massive-parallel memory-embedded SIMD matrix architecture to enable fast pipelined table-lookup coding. Since both arithmetic logical operation and table-lookup coding execute extremely fast on these architectures, efficient execution of encryption and decryption algorithms can be realized. Evaluation results of the CAM-less and CAM-enhanced massive-parallel SIMD matrix processor for the example of the Advanced Encryption Standard (AES), which is a widely-used cryptographic algorithm, show that a throughput of up to 2.19 Gbps becomes possible. This means that several standard data-storage transfer specifications, such as SD, CF (Compact Flash), USB (Universal Serial Bus) and SATA (Serial Advanced Technology Attachment) can be covered. Consequently, the massive-parallel SIMD matrix architecture is very suitable for private information protection in several data-storage media. A further advantage of the software based solution is the flexible update possibility of the implemented-cryptographic algorithm to a safer future algorithm. The massive-parallel memory-embedded SIMD matrix architecture (MTX and MX-2) is therefore a promising solution for integrated realization of real-time cryptographic algorithms with low power dissipation and small Si-area consumption.

  • A Simple Class of Binary Neural Networks and Logical Synthesis

    Yuta NAKAYAMA  Ryo ITO  Toshimichi SAITO  

     
    LETTER-Nonlinear Problems

      Vol:
    E94-A No:9
      Page(s):
    1856-1859

    This letter studies learning of the binary neural network and its relation to the logical synthesis. The network has the signum activation function and can approximate a desired Boolean function if parameters are selected suitably. In a parameter subspace the network is equivalent to the disjoint canonical form of the Boolean functions. Outside of the subspace, the network can have simpler structure than the canonical form where the simplicity is measured by the number of hidden neurons. In order to realize effective parameter setting, we present a learning algorithm based on the genetic algorithm. The algorithm uses the teacher signals as the initial kernel and tolerates a level of learning error. Performing basic numerical experiments, the algorithm efficiency is confirmed.

  • Cross Low-Dimension Pursuit for Sparse Signal Recovery from Incomplete Measurements Based on Permuted Block Diagonal Matrix

    Zaixing HE  Takahiro OGAWA  Miki HASEYAMA  

     
    PAPER-Digital Signal Processing

      Vol:
    E94-A No:9
      Page(s):
    1793-1803

    In this paper, a novel algorithm, Cross Low-dimension Pursuit, based on a new structured sparse matrix, Permuted Block Diagonal (PBD) matrix, is proposed in order to recover sparse signals from incomplete linear measurements. The main idea of the proposed method is using the PBD matrix to convert a high-dimension sparse recovery problem into two (or more) groups of highly low-dimension problems and crossly recover the entries of the original signal from them in an iterative way. By sampling a sufficiently sparse signal with a PBD matrix, the proposed algorithm can recover it efficiently. It has the following advantages over conventional algorithms: (1) low complexity, i.e., the algorithm has linear complexity, which is much lower than that of existing algorithms including greedy algorithms such as Orthogonal Matching Pursuit and (2) high recovery ability, i.e., the proposed algorithm can recover much less sparse signals than even 1-norm minimization algorithms. Moreover, we demonstrate both theoretically and empirically that the proposed algorithm can reliably recover a sparse signal from highly incomplete measurements.

  • High-Speed FPGA Implementation of the SHA-1 Hash Function

    Je-Hoon LEE  Sang-Choon KIM  Young-Jun SONG  

     
    LETTER-Cryptography and Information Security

      Vol:
    E94-A No:9
      Page(s):
    1873-1876

    This paper presents a high-speed SHA-1 implementation. Unlike the conventional unfolding transformation, the proposed unfolding transformation technique makes the combined hash operation blocks to have almost the same delay overhead regardless of the unfolding factor. It can achieve high throughput of SHA-1 implementation by avoiding the performance degradation caused by the first hash computation. We demonstrate the proposed SHA-1 architecture on a FPGA chip. From the experimental results, the SHA-1 architecture with unfolding factor 5 shows 1.17 Gbps. The proposed SHA-1 architecture can achieve about 31% performance improvements compared to its counterparts. Thus, the proposed SHA-1 can be applicable for the security of the high-speed but compact mobile appliances.

  • New Encoding Method of Parameter for Dynamic Encoding Algorithm for Searches (DEAS)

    Youngsu PARK  Jong-Wook KIM  Johwan KIM  Sang Woo KIM  

     
    PAPER-Numerical Analysis and Optimization

      Vol:
    E94-A No:9
      Page(s):
    1804-1816

    The dynamic encoding algorithm for searches (DEAS) is a recently developed algorithm that comprises a series of global optimization methods based on variable-length binary strings that represent real variables. It has been successfully applied to various optimization problems, exhibiting outstanding search efficiency and accuracy. Because DEAS manages binary strings or matrices, the decoding rules applied to the binary strings and the algorithm's structure determine the aspects of local search. The decoding rules used thus far in DEAS have some drawbacks in terms of efficiency and mathematical analysis. This paper proposes a new decoding rule and applies it to univariate DEAS (uDEAS), validating its performance against several benchmark functions. The overall optimization results of the modified uDEAS indicate that it outperforms other metaheuristic methods and obviously improves upon older versions of DEAS series.

  • The Marking Construction Problem of Petri Nets and Its Heuristic Algorithms

    Satoshi TAOKA  Toshimasa WATANABE  

     
    PAPER-Concurrent Systems

      Vol:
    E94-A No:9
      Page(s):
    1833-1841

    The marking construction problem (MCP) of Petri nets is defined as follows: “Given a Petri net N, an initial marking Mi and a target marking Mt, construct a marking that is closest to Mt among those which can be reached from Mi by firing transitions.” MCP includes the well-known marking reachability problem of Petri nets. MCP is known to be NP-hard, and we propose two schemas of heuristic algorithms: (i) not using any algorithm for the maximum legal firing sequence problem (MAX LFS) or (ii) using an algorithm for MAX LFS. Moreover, this paper proposes four pseudo-polynomial time algorithms: MCG and MCA for (i), and MCHFk and MC_feideq_a for (ii), where MCA (MC_feideq_a, respectively) is an improved version of MCG (MCHFk). Their performance is evaluated through results of computing experiment.

  • A New Method for Per-Flow Traffic Measurement

    MyungKeun YOON  

     
    LETTER-Network

      Vol:
    E94-B No:8
      Page(s):
    2386-2389

    Per-flow traffic measurement is essential for network management; billing, traffic engineering, mitigating denial of service attacks, to mention just a few. In this field, the fundamental problem is that the size of expensive SRAM is too small to hold traffic data from high-speed networks. In this paper, we propose a new method for per-flow traffic measurement, which is based on the virtual vector that was originally designed for the problem of spread estimation. We modify the original virtual vector and show that this simple change yields a highly effective per-flow traffic estimator. Experiments show that our proposed scheme outperforms the state-of-the-art method in terms of both processing time and space requirement.

  • Adaptive Noise Suppression Algorithm for Speech Signal Based on Stochastic System Theory

    Akira IKUTA  Hisako ORIMOTO  

     
    PAPER

      Vol:
    E94-A No:8
      Page(s):
    1618-1627

    Numerous noise suppression methods for speech signals have been developed up to now. In this paper, a new method to suppress noise in speech signals is proposed, which requires a single microphone only and doesn't need any priori-information on both noise spectrum and pitch. It works in the presence of noise with high amplitude and unknown direction of arrival. More specifically, an adaptive noise suppression algorithm applicable to real-life speech recognition is proposed without assuming the Gaussian white noise, which performs effectively even though the noise statistics and the fluctuation form of speech signal are unknown. The effectiveness of the proposed method is confirmed by applying it to real speech signals contaminated by noises.

  • Regularization of the RLS Algorithm

    Jacob BENESTY  Constantin PALEOLOGU  Silviu CIOCHIN  

     
    LETTER

      Vol:
    E94-A No:8
      Page(s):
    1628-1629

    Regularization plays a fundamental role in adaptive filtering. There are, very likely, many different ways to regularize an adaptive filter. In this letter, we propose one possible way to do it based on a condition that makes intuitively sense. From this condition, we show how to regularize the recursive least-squares (RLS) algorithm.

  • Design and Implementation of a Low-Complexity Reed-Solomon Decoder for Optical Communication Systems

    Ming-Der SHIEH  Yung-Kuei LU  

     
    PAPER-Computer System

      Vol:
    E94-D No:8
      Page(s):
    1557-1564

    A low-complexity Reed-Solomon (RS) decoder design based on the modified Euclidean (ME) algorithm proposed by Truong is presented in this paper. Low complexity is achieved by reformulating Truong's ME algorithm using the proposed polynomial manipulation scheme so that a more compact polynomial representation can be derived. Together with the developed folding scheme and simplified boundary cell, the resulting design effectively reduces the hardware complexity while meeting the throughput requirements of optical communication systems. Experimental results demonstrate that the developed RS(255, 239) decoder, implemented in the TSMC 0.18 µm process, can operate at up to 425 MHz and achieve a throughput rate of 3.4 Gbps with a total gate count of 11,759. Compared to related works, the proposed decoder has the lowest area requirement and the smallest area-time complexity.

  • Multi-Stage Decoding Scheme with Post-Processing for LDPC Codes to Lower the Error Floors

    Beomkyu SHIN  Hosung PARK  Jong-Seon NO  Habong CHUNG  

     
    LETTER-Fundamental Theories for Communications

      Vol:
    E94-B No:8
      Page(s):
    2375-2377

    In this letter, we propose a multi-stage decoding scheme with post-processing for low-density parity-check (LDPC) codes, which remedies the rapid performance degradation in the high signal-to-noise ratio (SNR) range known as error floor. In the proposed scheme, the unsuccessfully decoded words of the previous decoding stage are re-decoded by manipulating the received log-likelihood ratios (LLRs) of the properly selected variable nodes. Two effective criteria for selecting the probably erroneous variable nodes are also presented. Numerical results show that the proposed scheme can correct most of the unsuccessfully decoded words of the first stage having oscillatory behavior, which are regarded as a main cause of the error floor.

  • Re-Scheduling of Unit Commitment Based on Customers' Fuzzy Requirements for Power Reliability

    Bo WANG  You LI  Junzo WATADA  

     
    PAPER-Fundamentals of Information Systems

      Vol:
    E94-D No:7
      Page(s):
    1378-1385

    The development of the electricity market enables us to provide electricity of varied quality and price in order to fulfill power consumers' needs. Such customers choices should influence the process of adjusting power generation and spinning reserve, and, as a result, change the structure of a unit commitment optimization problem (UCP). To build a unit commitment model that considers customer choices, we employ fuzzy variables in this study to better characterize customer requirements and forecasted future power loads. To measure system reliability and determine the schedule of real power generation and spinning reserve, fuzzy Value-at-Risk (VaR) is utilized in building the model, which evaluates the peak values of power demands under given confidence levels. Based on the information obtained using fuzzy VaR, we proposed a heuristic algorithm called local convergence-averse binary particle swarm optimization (LCA-PSO) to solve the UCP. The proposed model and algorithm are used to analyze several test systems. Comparisons between the proposed algorithm and the conventional approaches show that the LCA-PSO performs better in finding the optimal solutions.

  • Processor Accelerator Customization through Data Flow Graph Exploration

    Kang ZHAO  Jinian BIAN  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E94-A No:7
      Page(s):
    1540-1552

    To reduce the huge search space when customizing accelerators for the application specific instruction-set processor (ASIP), this paper proposes an automated customization method based on the data flow graph exploration. This method integrates the instruction identification and selection using an iterative improvement strategy, which uses a seed-growth algorithm to select the valid patterns that can bring higher performance enhancement. The search space is reduced by considering the performance factors during the identification stage. The experimental results indicate that the proposed method is feasible enough compared to the previous exhaustive algorithms.

601-620hit(2137hit)