The search functionality is under construction.
The search functionality is under construction.

Keyword Search Result

[Keyword] algorithm(2137hit)

801-820hit(2137hit)

  • An Enhanced Front-End Algorithm for Reducing Channel Change Time in DVB-T System

    Inwhee JOE  Jongsung CHOI  

     
    LETTER-Broadcast Systems

      Vol:
    E92-B No:1
      Page(s):
    350-353

    To address the low performance for channel scanning in the DVB-T system, we propose an enhanced front-end algorithm in this paper. The proposed algorithm consists of Auto Scan and Normal Scan, which is a part of the tuning algorithm for front-end (tuner) drivers in the DVB-T receiver. The key idea is that the frequency offset is saved when performing Auto Scan in order to reduce the channel change time for Normal Scan. In addition, the results of a performance evaluation demonstrate that our enhanced front-end algorithm improves the performance of channel scanning significantly, as compared to the generic front-end algorithm.

  • Estimation of Reflection Coefficient and Surface Impedance from Absolute Values of the Near Field with Periodic Change

    Michinari SHIMODA  Masazumi MIYOSHI  Kazunori MATSUO  Yoshitada IYAMA  

     
    PAPER

      Vol:
    E92-C No:1
      Page(s):
    92-101

    An inverse scattering problem of estimating the reflection coefficient and the surface impedance from two sets of absolute values of the near field with periodic change is investigated. The problem is formulated in terms of a nonlinear simultaneous equations which is derived from the relation between the two sets of absolute values and the field defined by a finite summation of the modal functions by applying the Fourier analysis. The reflection coefficient is estimated by solving the equations by Newton's method through the successive algorithm with the increment of the number of truncation in the summation one after another. Numerical examples are given and the accuracy of the estimation is discussed.

  • A Variable Step Size Algorithm for Speech Noise Reduction Method Based on Noise Reconstruction System

    Naoto SASAOKA  Masatoshi WATANABE  Yoshio ITOH  Kensaku FUJII  

     
    PAPER-Digital Signal Processing

      Vol:
    E92-A No:1
      Page(s):
    244-251

    We have proposed a noise reduction method based on a noise reconstruction system (NRS). The NRS uses a linear prediction error filter (LPEF) and a noise reconstruction filter (NRF) which estimates background noise by system identification. In case a fixed step size for updating tap coefficients of the NRF is used, it is difficult to reduce background noise while maintaining the high quality of enhanced speech. In order to solve the problem, a variable step size is proposed. It makes use of cross-correlation between an input signal and an enhanced speech signal. In a speech section, a variable step size becomes small so as not to estimate speech, on the other hand, large to track the background noise in a non-speech section.

  • A High Performance Partially-Parallel Irregular LDPC Decoder Based on Sum-Delta Message Passing Schedule

    Wen JI  Yuta ABE  Takeshi IKENAGA  Satoshi GOTO  

     
    PAPER-Embedded, Real-Time and Reconfigurable Systems

      Vol:
    E91-A No:12
      Page(s):
    3622-3629

    In this paper, we propose a partially-parallel irregular LDPC decoder based on IEEE 802.11n standard targeting high throughput and small area applications. The design is based on a novel sum-delta message passing algorithm characterized as follows: (i) Decoding throughput is greatly improved by utilizing the difference value between the updated and the original value to remove redundant computations. (ii) Registers and memory are optimized to store only the frequently used messages to decrease the hardware cost. (iii) Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed up the message passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200 MHz, with 11% area reduction. The synthesis result also demonstrates the competitiveness to the fully-parallel regular LDPC decoders in terms of the tradeoff between throughput, area and power.

  • A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processors

    Vu Manh TUAN  Hideharu AMANO  

     
    PAPER-Computer Systems

      Vol:
    E91-D No:12
      Page(s):
    2793-2803

    Task preemption is a critical mechanism for building an effective multi-tasking environment on dynamically reconfigurable processors. When a task is preempted, its necessary state information must be correctly preserved in order for the task to be resumed later. Not only do coarse-grained Dynamically Reconfigurable Processing Array (DRPAs) devices have different architectures using a variety of development tools, but the great amount of state data of hardware tasks executing on such devices are usually distributed on many different storage elements. To address these difficulties, this paper aims at studying a general method for capturing the state data of hardware tasks targeting coarse-grained DRPAs. Based on resource usage, algorithms for identifying preemption points and inserting preemption states subject to user-specified preemption latency are proposed. Moreover, a modification to automatically incorporate proposed steps into the system design flow is also discussed. The performance degradation caused by additional preemption states is minimized by allowing preemption only at predefined points where demanded resources are small. The evaluation result using a model based on NEC Electronics' DRP-1 shows that the proposed method can produce preemption points satisfying a given preemption latency with reasonable hardware overhead (from 6% to 15%).

  • Efficient Hybrid Grid Synthesis Method Based on Genetic Algorithm for Power/Ground Network Optimization with Dynamic Signal Consideration

    Yun YANG  Shinji KIMURA  

     
    PAPER-Physical Level Design

      Vol:
    E91-A No:12
      Page(s):
    3431-3442

    This paper proposes an efficient design algorithm for power/ground (P/G) network synthesis with dynamic signal consideration, which is mainly caused by Ldi/dt noise and Cdv/dt decoupling capacitance (DECAP) current in the distribution network. To deal with the nonlinear global optimization under synthesis constraints directly, the genetic algorithm (GA) is introduced. The proposed GA-based synthesis method can avoid the linear transformation loss and the restraint condition complexity in current SLP, SQP, ICG, and random-walk methods. In the proposed Hybrid Grid Synthesis algorithm, the dynamic signal is simulated in the gene disturbance process, and Trapezoidal Modified Euler (TME) method is introduced to realize the precise dynamic time step process. We also use a hybrid-SLP method to reduce the genetic execute time and increase the network synthesis efficiency. Experimental results on given power distribution network show the reduction on layout area and execution time compared with current P/G network synthesis methods.

  • Affine Projection Algorithm with Improved Data-Selective Method Using the Condition Number

    Sung Jun BAN  Chang Woo LEE  Sang Woo KIM  

     
    LETTER-Digital Signal Processing

      Vol:
    E91-A No:12
      Page(s):
    3820-3823

    Recently, a data-selective method has been proposed to achieve low misalignment in affine projection algorithm (APA) by keeping the condition number of an input data matrix small. We present an improved method, and a complexity reduction algorithm for the APA with the data-selective method. Experimental results show that the proposed algorithm has lower misalignment and a lower condition number for an input data matrix than both the conventional APA and the APA with the previous data-selective method.

  • Construction of Scalable 2-D Multi-Weight Optical Orthogonal Codes for Optical CDMA Networks

    Yong-Chun PIAO  Jinwoo CHOE  Wonjin SUNG  Dong-Joon SHIN  

     
    LETTER-Fundamental Theories for Communications

      Vol:
    E91-B No:12
      Page(s):
    3990-3993

    In this letter, we propose combinatorial and search construction methods of 2-D multi-weight optical orthogonal codes (OOCs) with autocorrelation 0 and crosscorrelation 1, called multi-weight single or no pulse per row (MSNPR) codes. An upper bound on the size of MSNPR codes is derived and the performance of MSNPR codes is compared to those of other OOCs in terms of the bit error rate (BER) and evaluated using blocking probability. It is also demonstrated that the MSNPR codes can be flexibly constructed for different applications, providing the scalability to optical CDMA networks.

  • A Novel Fast-Lock-in Digitally Controlled Phase-Locked Loop

    Xin CHEN  Jun YANG  Long-xing SHI  

     
    LETTER-Integrated Electronics

      Vol:
    E91-C No:12
      Page(s):
    1971-1975

    A novel fast lock-in digitally controlled phase-locked loop (DCPLL) is proposed in this letter. This DCPLL adopts a novel frequency search algorithm to reduce the lock-in time. Furthermore, to reduce the power consumption, the frequency divider is reused as a frequency detector during the frequency acquisition, and reused as a time-to-digital converter module during the phase acquisition. To verify the proposed algorithm and architecture, a DCPLL design is implemented by SMIC 0.18 µm 1P6M CMOS technology. The Spice simulation results show that the DCPLL can achieve frequency acquisition in 3 reference cycles and complete phase acquisition in 11 reference cycles when locking to 200 MHz. The corresponding power consumption of DCPLL is 3.71 mW.

  • Component Reduction for Gaussian Mixture Models

    Kumiko MAEBASHI  Nobuo SUEMATSU  Akira HAYASHI  

     
    PAPER-Pattern Recognition

      Vol:
    E91-D No:12
      Page(s):
    2846-2853

    The mixture modeling framework is widely used in many applications. In this paper, we propose a component reduction technique, that collapses a Gaussian mixture model into a Gaussian mixture with fewer components. The EM (Expectation-Maximization) algorithm is usually used to fit a mixture model to data. Our algorithm is derived by extending mixture model learning using the EM-algorithm. In this extension, a difficulty arises from the fact that some crucial quantities cannot be evaluated analytically. We overcome this difficulty by introducing an effective approximation. The effectiveness of our algorithm is demonstrated by applying it to a simple synthetic component reduction task and a phoneme clustering problem.

  • Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages

    Hasitha Muthumala WAIDYASOORIYA  Masanori HARIYAMA  Michitaka KAMEYAMA  

     
    PAPER-High-Level Synthesis and System-Level Design

      Vol:
    E91-A No:12
      Page(s):
    3596-3606

    This paper presents a high-level synthesis approach to minimize the total power consumption in behavioral synthesis under time and area constraints. The proposed method has two stages, functional unit (FU) energy optimization and interconnect energy optimization. In the first stage, active and inactive energies of the FUs are optimized using a multiple supply and threshold voltage scheme. Genetic algorithm (GA) based simultaneous assignment of supply and threshold voltages and module selection is proposed. The proposed GA based searching method can be used in large size problems to find a near-optimal solution in a reasonable time. In the second stage, interconnects are simplified by increasing their sharing. This is done by exploiting similar data transfer patterns among FUs. The proposed method is evaluated for several benchmarks under 90 nm CMOS technology. The experimental results show that more than 40% of energy savings can be achieved by our proposed method.

  • High Throughput VLSI Architecture of a Fast Mode Decision Algorithm for H.264/AVC Intra Encoding

    Tianruo ZHANG  Guifen TIAN  Takeshi IKENAGA  Satoshi GOTO  

     
    PAPER-Embedded, Real-Time and Reconfigurable Systems

      Vol:
    E91-A No:12
      Page(s):
    3630-3637

    Intra coding in H.264/AVC has significantly enhanced video compression efficiency. However, computation complexity increases by the rate-distortion (RD) based mode decision. This paper proposes a novel fast mode decision algorithm in H.264/AVC intra prediction and its VLSI architecture. A novel edge-detection pattern is proposed and both edge-detection technique and spatial mode prediction technique are combined together to reduce the number of intra 44 candidate modes from 9 to an average of 2.50. VLSI architecture of intra mode decision module is designed with TSMC 0.18 µm CMOS technology. The maximum frequency of 285 MHz is achieved and 13.1k NAND gates are required. High frequency, efficient processing cycle reduction and small area make this design to be an excellent accelerator for HDTV 1080p@30 fps real time encoder.

  • Design of an Area-Efficient and Low-Power NoC Architecture Using a Hybrid Network Topology

    Woo Joo KIM  Sun Young HWANG  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E91-A No:11
      Page(s):
    3297-3303

    This paper proposes a novel hybrid NoC structure and a dynamic job distribution algorithm which can reduce system area and power consumption by reducing packet drop rate for various multimedia applications. The proposed NoC adopts different network structures between sub-clusters. Network structure is determined by profiling application program so that packet drop rate can be minimized. The proposed job distribution algorithm assigns every job to the sub-cluster where packet drop rate can be minimized for each multimedia application program. The proposed scheme targets multimedia applications frequently used in modern embedded systems, such as MPEG4 and MP3 decoders, GPS positioning systems, and OFDM demodulators. Experimental results show that packet drop rate was reduced by 31.6% on the average, when compared to complex network structure topologies consisting of sub-clusters of same topology. Chip area and power consumption were reduced by 16.0% and 34.0%, respectively.

  • Optimal Sensor Deployment for Wireless Surveillance Sensor Networks by a Hybrid Steady-State Genetic Algorithm

    Jae-Hyun SEO  Yong-Hyuk KIM  Hwang-Bin RYOU  Si-Ho CHA  Minho JO  

     
    PAPER

      Vol:
    E91-B No:11
      Page(s):
    3534-3543

    An important objective of surveillance sensor networks is to effectively monitor the environment, and detect, localize, and classify targets of interest. The optimal sensor placement enables us to minimize manpower and time, to acquire accurate information on target situation and movement, and to rapidly change tactics in the dynamic field. Most of previous researches regarding the sensor deployment have been conducted without considering practical input factors. Thus in this paper, we apply more real-world input factors such as sensor capabilities, terrain features, target identification, and direction of target movements to the sensor placement problem. We propose a novel and efficient hybrid steady-state genetic algorithm giving low computational overhead as well as optimal sensor placement for enhancing surveillance capability to monitor and locate target vehicles. The proposed algorithm introduces new two-dimensional geographic crossover and mutation. By using a new simulator adopting the proposed genetic algorithm developed in this paper, we demonstrate successful applications to the wireless real-world surveillance sensor placement problem giving very high detection and classification rates, 97.5% and 87.4%, respectively.

  • 2-Dimensional Imaging of Human Bodies with UWB Radar Using Approximately Uniform Walking Motion along a Straight Line with the SEABED Algorithm

    Takuya SAKAMOTO  Toru SATO  

     
    PAPER-Sensing

      Vol:
    E91-B No:11
      Page(s):
    3695-3703

    UWB (Ultra Wide-Band) pulse radar is a promising candidate for surveillance systems designed to prevent crimes and terror-related activities. The high-speed SEABED (Shape Estimation Algorithm based on BST and Extraction of Directly scattered waves) imaging algorithm, is used in the application of UWB pulse radar in fields that require realtime operations. The SEABED algorithm assumes that omni-directional antennas are scanned to observe the scattered electric field in each location. However, for surveillance systems, antenna scanning is impractical because it restricts the setting places of the devices. In this paper, movement of a body is used to replace antenna scanning. The instantaneous velocity of any given motion is an unknown variable that changes as a function of time. A pair of antennas is used to analyze delay time to estimate the unknown motion. We propose a new algorithm to estimate the shape of a human body using data obtained from a human body passing stationary antennas.

  • Precise DOA Estimation Using SAGE Algorithm with a Cylindrical Array

    Masaki TAKANASHI  Toshihiko NISHIMURA  Yasutaka OGAWA  Takeo OHGANE  

     
    LETTER-Antennas and Propagation

      Vol:
    E91-B No:11
      Page(s):
    3784-3787

    A uniform circular array (UCA) is a well-known array configuration which can accomplish estimation of 360 field of view with identical accuracy. However, a UCA cannot estimate coherent signals because we cannot apply the SSP owing to the structure of UCA. Although a variety of studies on UCA in coherent multipath environments have been done, it is impossible to estimate the DOA of coherent signals with different incident polar angles. Then, we have proposed Root-MUSIC algorithm with a cylindrical array. However, the estimation performance is degraded when incident signals arrive with close polar angles. To solve this problem, in the letter, we propose to use SAGE algorithm with a cylindrical array. Here, we adopt a CLA Root-MUSIC for the initial estimation and decompose two-dimensional search to double one-dimensional search to reduce the calculation load. The results show that the proposal achieves high resolution with low complexity.

  • Non-recursive Discrete Periodized Wavelet Transform Using Segment Accumulation Algorithm and Reversible Round-Off Approach

    Chin-Feng TSAI  Huan-Sheng WANG  King-Chu HUNG  Shih-Chang HSIA  

     
    PAPER-VLSI Systems

      Vol:
    E91-D No:11
      Page(s):
    2666-2674

    Wavelet-based features with simplicity and high efficacy have been used in many pattern recognition (PR) applications. These features are usually generated from the wavelet coefficients of coarse levels (i.e., high octaves) in the discrete periodized wavelet transform (DPWT). In this paper, a new 1-D non-recursive DPWT (NRDPWT) is presented for real-time high octave decomposition. The new 1-D NRDPWT referred to as the 1-D RRO-NRDPWT can overcome the word-length-growth (WLG) effect based on two strategies, resisting error propagation and applying a reversible round-off linear transformation (RROLT) theorem. Finite precision performance analysis is also taken to study the word length suppression efficiency and the feature efficacy in breast lesion classification on ultrasonic images. For the realization of high octave decomposition, a segment accumulation algorithm (SAA) is also presented. The SAA is a new folding technique that can reduce multipliers and adders dramatically without the cost of increasing latency.

  • Improving VoIP Quality Using Silence Description Packets in the Jitter Buffer

    Younchan JUNG  J. William ATWOOD  Hans-Jurgen ZEPERNICK  

     
    LETTER-Internet

      Vol:
    E91-B No:11
      Page(s):
    3719-3721

    The basic playout scheme (BAS) is designed not to take into account network impairment information during silence periods. We propose a jitter-robust playout mechanism (RST), which uses silence description (SID) packets. The lateness loss percentages are compared between the BAS and the RST algorithms. We report that the accuracy of the playout schedule calculation in the BAS is getting worse as the previous silence interval increases and our proposed RST algorithm is more effective in removing high jitter than the BAS. Under high jitter Internet conditions, the accuracy of the estimates and therefore the resulting of VoIP playout quality can be significantly improved by using the SID packets in the playout schedule recalculation.

  • Interference Detection Based on AIC Using EM Algorithm for UWB MB-OFDM Systems

    Masahiro FUJII  Atsushi MINAKAWA  Yu WATANABE  Makoto ITAMI  Kohji ITOH  

     
    PAPER

      Vol:
    E91-A No:11
      Page(s):
    3130-3139

    In this paper, we propose a new algorithm to detect the presence of narrow band interference signals on the band of an Ultra Wide-Band (UWB) system when the UWB spectrum overlaps the bands of other narrow band wireless services. In our proposed algorithm for an UWB Multi-Band Orthogonal Frequency Division Multiplexing (MB-OFDM) system, an appropriate model is selected from the assumed interference models based on the Akaike Information Criterion (AIC) which is an explicit theoretic criterion and a measure of fit of the model. The proposed algorithm does not need a priori information on the interference signals except that we can reduce a computational complexity to implement the algorithm if we have knowledge of the bands of the interference signals. Furthermore, we introduce the Expectation Maximization (EM) algorithm to our algorithm in order to estimate the transmitted signals and the interference signals simultaneously. The proposed algorithm may not require the pilot symbols in the assumed UWB system to detect the presence of other systems. By computer simulations, we show that the proposed algorithm validly detects the presence of interference signals on the UWB band.

  • Finding Frequent Closed Itemsets in Sliding Window in Linear Time

    Junbo CHEN  Bo ZHOU  Lu CHEN  Xinyu WANG  Yiqun DING  

     
    PAPER-Data Mining

      Vol:
    E91-D No:10
      Page(s):
    2406-2418

    One of the most well-studied problems in data mining is computing the collection of frequent itemsets in large transactional databases. Since the introduction of the famous Apriori algorithm [14], many others have been proposed to find the frequent itemsets. Among such algorithms, the approach of mining closed itemsets has raised much interest in data mining community. The algorithms taking this approach include TITANIC [8], CLOSET+ [6], DCI-Closed [4], FCI-Stream [3], GC-Tree [5], TGC-Tree [16] etc. Among these algorithms, FCI-Stream, GC-Tree and TGC-Tree are online algorithms work under sliding window environments. By the performance evaluation in [16], GC-Tree [15] is the fastest one. In this paper, an improved algorithm based on GC-Tree is proposed, the computational complexity of which is proved to be a linear combination of the average transaction size and the average closed itemset size. The algorithm is based on the essential theorem presented in Sect. 4.2. Empirically, the new algorithm is several orders of magnitude faster than the state of art algorithm, GC-Tree.

801-820hit(2137hit)