In this letter we give a lower bound on the worst-case time complexity of Dijkstra's three-state mutual exclusion algorithm by specifying a concrete behavior of the algorithm. We also show that our result is more accurate than the known best bound.

In this letter the complexity of factoring an α-LSBS modulus is analyzed. This gives an improvement on the lower bound of the previous results.

In this paper, we consider a problem of assigning n independent tasks onto m identical processors in such a way that the overall execution time of the tasks will be minimized. Unlike conventional task assignment problem, we assume that the execution time of each task is not fixed in advance, and merely upper and lower bounds of the execution time are given at the compile time. In the following, we first provide a theoretical analysis of several conventional scheduling policies in terms of the worst case slowdown compared with the outcome of an optimal off-line scheduling policy. It is shown that the best known algorithm in the literature achieves a worst case performance ratio of 1 + 1/f(n) where f(n) = O(n2/3) for any fixed m, which approaches to one by increasing n to the infinity. We then propose a new scheme that achieves better worst case ratio of 1 + 1/g(n) where g(n) = Θ (n/log n) for any fixed m, which approaches to one more quickly than previous schemes.

IEEE 802.11 MAC protocol for medium access control in wireless Local Area Networks (LANs) is the de facto standard for wireless ad hoc networks. However, it does not perform well in terms of fairness, delay and throughput specially, in multihop networks. The problem is due to both the MAC and link layer contentions. Many research papers have been published in these fields. Among them, a modification of IEEE 802.11 MAC protocol was proposed to achieve per-node fairness, but modifications to the original MAC layer requires a change of hardware, therefore, it is difficult to implement. Moreover, it fails to solve the per-flow unfairness problem. In this paper, we propose a new scheduling method, Probabilistic Control on Round robin Queue (PCRQ) scheduling, aiming to achieve per-flow fairness in multihop ad hoc networks. PCRQ scheduling in the link layer is proposed without modifying IEEE 802.11 MAC protocol. Our proposed method achieves good performance results in both UDP and TCP traffic.

This paper introduces a multilayer traffic network model and traffic network clustering method for solving the route selection problem (RSP) in car navigation system (CNS). The purpose of the proposed method is to reduce the computation time of route selection substantially with acceptable loss of accuracy by preprocessing the large size traffic network into new network form. The proposed approach further preprocesses the traffic network than the traditional hierarchical network method by clustering method. The traffic network clustering considers two criteria. We specify a genetic clustering algorithm for traffic network clustering and use NSGA-II for calculating the multiple objective Pareto optimal set. The proposed method can overcome the size limitations when solving route selection in CNS. Solutions provided by the proposed algorithm are compared with the optimal solutions to analyze and quantify the loss of accuracy.

Weighted graph matching is computationally challenging due to the combinatorial nature of the set of permutations. In this paper, a new relaxation approach to weighted graph matching is proposed, by which a new matching algorithm, named alternate iteration algorithm, is designed. It is proved that the algorithm proposed is locally convergent. Experiments are presented to show the effectiveness of the proposed algorithm.

The line-based method has been one of the most commonly-used methods of hardware implementation of two-dimensional (2D) discrete wavelet transform (DWT). However, data buffer is required between the row DWT processor and the column DWT processor to solve the data flow mismatch, which increases the on-chip memory size and the output latency. Since the incompatible data flow is induced from the intrinsic property of adopted lifting-based algorithm, a decomposed lifting algorithm (DLA) is presented by rearranging the data path of lifting steps to ensure that image data is processed in raster scan manner in row processor and column processor. Theoretical analysis indicates that the precision issue of DLA outperforms other lifting-based algorithms in terms of round-off noise and internal word-length. A memory-efficient and high-performance line-based architecture is proposed based on DLA without the implementation of data buffer. For an N M image, only 2N internal memory is required for 5/3 filter and 4N of that is required for 9/7 filter to perform 2D DWT, where N and M indicate the width and height of an image. Compared with related 2D DWT architectures, the size of on-chip memory is reduced significantly under the same arithmetic cost, memory bandwidth and timing constraint. This design was implemented in SMIC 0.18 µm CMOS logic fabrication with 32 kbits dual-port RAM and 20 K equivalent 2-input NAND gates in a 1.00 mm 1.00 mm die, which can process 512 512 image under 100 MHz.

In this paper, we present a low complexity, yet accurate adaptive algorithm for the tracking of two-dimensional (2-D) direction of arrival (DOAs) based on a uniform rectangular array (URA). The new algorithm is a novel hybrid of tracking and beamforming processes by making use of three stages of one-dimensional (1-D) DOA tracking algorithms -- in a hierarchical tree structure -- to determine the two DOA components iteratively in a coarse-fine manner. In between every other 1-D DOA tracking algorithm, a complementary orthogonal beamforming process is invoked to partition the incoming signals into appropriate groups to enhance the tracking accuracy. Since the new algorithm only involves the 1-D subspace-based DOA tracking algorithm, the overall complexity is substantially less than the direct two-dimensional (2-D) extension of the existing 1-D DOA tracking algorithms, which requires an update of higher-dimensional vectors followed by a higher-dimensional eigendecomposition or a 2-D search. Furthermore, with the tree-structured DOA tracking scheme, the tracked 2-D DOA components are automatically paired without extra computational overhead. Furnished simulations show that the new algorithm can provide satisfactory tracking performance in various scenarios.

A direct short proof of Horiguchi's formula for error values in alternant codes is provided. Horiguchi's formula employs only output polynomials of Berlekamp-Massey algorithm, which has less computational complexity than extended Euclidean algorithm for decoding alternant codes. As an application of our proof, we provide an explicit formula for the generator and parity check matrices of alternant codes and their singly- and doubly-extended codes.

A linear consecutive-k-out-of-n: F system is an ordered sequence of n components. This system fails if, and only if, k or more consecutive components fail. Optimal arrangement is one of the main problems for such kind of system. In this problem, we want to obtain an optimal arrangement of components to maximize system reliability, when all components of the system need not have equal component failure probability and all components are mutually statistically independent. As n becomes large, however, the amount of calculation would be too much to solve within a reasonable computing time even by using a high-performance computer. Hanafusa and Yamamoto proposed applying Genetic Algorithm (GA) to obtain quasi optimal arrangement in a linear consecutive-k-out-of-n: F system. GA is known as a powerful tool for solving many optimization problems. They also proposed ordinal representation, which produces only arrangements satisfying the necessary conditions for optimal arrangements and eliminates redundant arrangements with same system reliabilities produced by reversal of certain arrangements. In this paper, we propose an efficient GA. We have modified the previous work mentioned above to allocate components with low failure probabilities, that is to say reliable components, at equal intervals, because such arrangements seem to have relatively high system reliabilities. Through the numerical experiments, we observed that our proposed GA with interval k provides better solutions than the previous work for the most cases.

Recently, it has become important to rapidly detect human subjects buried under collapsed houses, rubble and soil due to earthquakes and avalanches to reduce the casualties in a disaster. Such detection systems have already been developed as one kind of microwave displacement sensors that are based on phase difference generated by the motion of the subject's breast. Because almost all the systems consist of single transmitter and receiver pair, it is difficult to rapidly scan a wide area. In this paper, we propose a single-frequency multistatic radar system to detect breathing human subjects which exist in the area surrounded by the transmitting and receiving array. The vibrating targets can be localized by the MUSIC algorithm with the complex amplitude in the Doppler frequency. This algorithm is validated by the simulated signals synthesized with a rigorous solution of a dielectric spherical target model. We show experimental 3D localization results using a developed multistatic Doppler radar system around 250 MHz.

A method using genetic algorithms for path generation have been proposed; however, this method is limited to particular applications, and there are limitations on the types of paths that can be represented. This paper therefore proposes a path generation method that is applicable to more general-purpose applications compared to previous methods based on a new design of the genotype used in the genetic algorithm.

A task that suspends itself to wait for an I/O completion or to wait for an event from another node in distributed environments is called an I/O blocking task. Conventional hard real-time scheduling theories use framework of rate monotonic analysis (RMA) to schedule such I/O blocking tasks. However, most of them are pessimistic. In this paper, we propose effective algorithms that can schedule a task set which has I/O blocking tasks under dynamic priority assignment. We present a new critical instant theorem for the multi-frame task set under dynamic priority assignment. The schedulability is analyzed under the new critical instant theorem. For the schedulability analysis, this paper presents saturation summation which is used to calculate the maximum interference function (MIF). With saturation summation, the schedulability of a task set having I/O blocking tasks can be analyzed more accurately. We propose an algorithm which is called Frame Laxity Monotonic Scheduling (FLMS). A genetic algorithm (GA) is also applied. From our experiments, we can conclude that FLMS can significantly reduce the calculation time, and GA can improve task schedulability ratio more than is possible with FLMS.

In this paper, we analyze the extended real-time Polling Service (ertPS) algorithm in IEEE 802.16e systems, which is designed to support Voice-over-Internet-Protocol (VoIP) services with data packets of various sizes and silence suppression. The analysis uses a two-dimensional Markov Chain, where the grant size and the voice packet state are considered, and an approximation formula for the total throughput in the ertPS algorithm is derived. Next, to improve the performance of the ertPS algorithm, we propose an enhanced uplink resource allocation algorithm, called the e 2rtPS algorithm, for VoIP services in IEEE 802.16e systems. The e 2rtPS algorithm considers the queue status information and tries to alleviate the queue congestion as soon as possible by using remaining network resources. Numerical results are provided to show the accuracy of the approximation analysis for the ertPS algorithm and to verify the effectiveness of the e 2rtPS algorithm.

The electromagnetic fields emitted from an electrostatic discharge (ESD) event occurring between charged metals cause seriously damage high-tech equipment. In order to clarify the generation mechanism of such ESD fields and also to reduce them, we previously proposed a finite-difference time-domain (FDTD) algorithm based on a delta-gap feeding method and a frequency dispersion characteristic formula (Naito's formula) of ferrite material for simulating the ESD fields due to a spark between the charged metals with ferrite core attachment. In the present study, by integrating the above FDTD algorithm and a spark-resistance formula, we simulated both of the ESD itself and the resultant fields for the metal bars with ferrite core attachment, and demonstrated that the core attachment close to the spark gap suppresses the magnetic field level. This finding was also validated via 6-GHz wide-band measurement of the magnetic near-field.

This paper presents a high-throughput bit-serial low-density parity-check (LDPC) decoder that uses an asynchronous interleaver. Since consecutive log-likelihood message values on the interleaver are similar, node computations are continuously performed by using the most recently arrived messages without significantly affecting bit-error rate (BER) performance. In the asynchronous interleaver, each message's arrival rate is based on the delay due to the wire length, so that the decoding throughput is not restricted by the worst-case latency, which results in a higher average rate of computation. Moreover, the use of a multiple-valued data representation makes it possible to multiplex control signals and data from mutual nodes, thus minimizing the number of handshaking steps in the asynchronous interleaver and eliminating the clock signal entirely. As a result, the decoding throughput becomes 1.3 times faster than that of a bit-serial synchronous decoder under a 90 nm CMOS technology, at a comparable BER.

This paper analyzes frequency tracking characteristics of a complex-coefficient adaptive infinite impulse response (IIR) notch filter with a simplified gradient-based algorithm. The input signal to the complex notch filter is a complex linear chirp embedded in a complex zero-mean white Gaussian noise. The analysis starts with derivation of a first-order real-coefficient difference equation with respect to steady-state instantaneous frequency tracking error. Closed-form expression for frequency tracking mean square error (MSE) is then derived from the difference equation. Lastly, closed-form expressions for optimum notch bandwidth coefficient and step size constant that minimize the frequency tracking MSE are derived. Computer simulations are presented to validate the analysis.

The All-Pairs Shortest Paths (APSP) problem is a graph problem which can be solved by a three-nested loop program. The Cell Broadband Engine (Cell/B.E.) is a heterogeneous multi-core processor that offers the high single precision floating-point performance. In this paper, a solution of the APSP problem on the Cell/B.E. is presented. To maximize the performance of the Cell/B.E., a blocked algorithm for the APSP problem is used. The blocked algorithm enables reuse of data in registers and utilizes the memory hierarchy. We also describe several optimization techniques for effective implementation of the APSP problem on the Cell/B.E. The Cell/B.E. achieves the performance of 8.45 Gflop/s for the APSP problem by using one SPE and 50.6 Gflop/s by using six SPEs.

Wireless ad hoc networks have fundamentally altered today's battlefield, with applications ranging from unmanned air vehicles to randomly deployed sensor networks. Security and vulnerabilities in wireless ad hoc networks have been considered at different layers, and many attack strategies have been proposed, including denial of service (DoS) through the intelligent jamming of the most critical packet types of flows in a network. This paper investigates the effectiveness of intelligent jamming in wireless ad hoc networks using the Dynamic Source Routing (DSR) and TCP protocols and introduces an intelligent classifier to facilitate the jamming of such networks. Assuming encrypted packet headers and contents, our classifier is based solely on the observable characteristics of size, inter-arrival timing, and direction and classifies packets with up to 99.4% accuracy in our experiments.

Testing and diagnosis techniques play a key role in the advance of semiconductor memory technology. The challenge of failure detection has created intensive investigation on efficient testing and diagnosis algorithm for better fault coverage and diagnostic resolution. At present, March test algorithm is used to detect and diagnose all faults related to Random Access Memories. However, the test and diagnosis process are mainly done manually. Due to this, a systematic approach for developing and evaluating memory test algorithm is required. This work is focused on incorporating the March based test algorithm using a software simulator tool for implementing a fast and systematic memory testing algorithm. The simulator allows a user through a GUI to select a March based test algorithm depending on the desired fault coverage and diagnostic resolution. Experimental results show that using the simulator for testing is more efficient than that of the traditional testing algorithm. This new simulator makes it possible for a detailed list of stuck-at faults, transition faults and coupling faults covered by each algorithm and its percentage to be displayed after a set of test algorithms has been chosen. The percentage of diagnostic resolution is also displayed. This proves that the simulator reduces the trade-off between test time, fault coverage and diagnostic resolution. Moreover, the chosen algorithm can be applied to incorporate with memory built-in self-test and diagnosis, to have a better fault coverage and diagnostic resolution. Universities and industry involved in memory Built-in-Self test, Built-in-Self repair and Built-in-Self diagnose will benefit by saving a few years on researching an efficient algorithm to be implemented in their designs.