Network function virtualization (NFV) enables network operators to flexibly provide diverse virtualized functions for services such as Internet of things (IoT) and mobile applications. To meet multiple quality of service (QoS) requirements against time-varying network environments, infrastructure providers must dynamically adjust the amount of computational resources, such as CPU, assigned to virtual network functions (VNFs). To provide agile resource control and adaptiveness, predicting the virtual server load via machine learning technologies is an effective approach to the proactive control of network systems. In this paper, we propose an adjustment mechanism for regressors based on forgetting and dynamic ensemble executed in a shorter time than that of our previous work. The framework includes a reducing training data method based on sparse model regression. By making a short list of training data derived from the sparse regression model, the relearning time can be reduced to about 57% without degrading provisioning accuracy.

Controller area network (CAN) has been widely adopted as an in-vehicle communications standard. CAN with flexible data-rate (CAN FD) is defined in the ISO standards to achieve higher data rates than the legacy CAN. A number of CAN nodes can be connected by a single transmission medium, i.e. CAN enables us to constitute cost-effective bus-topology networks. CAN puts carrier sense multiple access with collision resolution (CSMA/CR) into practice by using bit-wise arbitration based on wired logical AND in the physical layer. The most prioritized message is delivered without interruption if two or more CAN nodes transmit messages at the same time due to the bit-wise arbitration. However, the scalability of CAN networks suffers from ringing caused by the signaling mechanism establishing the wired logical AND. We need to reduce networking material in a car in order to reduce the car weight, save the fuel and the cost, and develop a sustainable society by establishing more scalable CAN networks. In this paper, we show a reduced wiring technology for CAN to enhance the network scalability and the cost efficiency.

With the development of silicon-based Nano-photonics, Optical Network on Chip (ONoC) is, due to its high bandwidth and low latency, becoming an important choice for future multi-core networks. As a key ONoC technology, the arbitration scheme should provide differential arbitration service with high throughput and low latency for various types and priorities of traffic in CMPs. In this work, we propose a fast hierarchical arbitration scheme based on multi-level priority QoS. First, given multi-priority data buffer queue, arbiters provide differential transmissions with fair service for all nodes and guarantee the max-transmit-delay and min-communication-bandwidth for all queues. Second, arbiter adopts the transmit bound resource reservation scheme to reserve time slots for all nodes fairly, thereby achieving a throughput of 100%. Third, we propose fast arbitration with a layout of fast optical arbitration channels (FOACs) to reduce the arbitration period, thereby reducing packet transmitting delay. Simulation results show that with our hierarchical arbitration scheme, all nodes are allocated almost equal service access probability under various traffic patterns; thus, the min-communication-bandwidth and max-transmit-delay is guaranteed to be 5% and 80 cycles, respectively, under the overload demands. This scheme improves throughput by 17% compared to FeatherWeight under a self-similar traffic pattern and decreases arbitration delay by 15% compare to 2-pass arbitration, incurring a total power overhead of 5%.

Financial exchanges provide market data feeds to update their members about changes in the market. Feed messages are often used in time-critical automated trading applications, and two identical feeds (A and B feeds) are provided in order to reduce message loss. A key challenge is to support A/B line arbitration efficiently to compensate for missing packets, while offering flexibility for various operational modes such as prioritising for low latency or for high data reliability. This paper presents a reconfigurable acceleration approach for A/B arbitration operating at the network level, capable of supporting any messaging protocol. Two modes of operation are provided simultaneously: one prioritising low latency, and one prioritising high reliability with three dynamically configurable windowing methods. We also present a model for message feed processing latencies that is useful for evaluating scalability in future applications. We outline a new low latency, high throughput architecture and demonstrate a cycle-accurate testing framework to measure the actual latency of packets within the FPGA. We implement and compare the performance of the NASDAQ TotalView-ITCH, OPRA and ARCA market data feed protocols using a Xilinx Virtex-6 FPGA. For high reliability messages we achieve latencies of 42ns for TotalView-ITCH and 36.75ns for OPRA and ARCA. 6ns and 5.25ns are obtained for low latency messages. The most resource intensive protocol, TotalView-ITCH, is also implemented in a Xilinx Virtex-5 FPGA within a network interface card; it is used to validate our approach with real market data. We offer latencies 10 times lower than an FPGA-based commercial design and 4.1 times lower than the hardware-accelerated IBM PowerEN processor, with throughputs more than double the required 10Gbps line rate.

To reduce RFID tag identification delay, we propose a novel Dynamic Splitting protocol (DS) which is an improvement of the Query tree protocol (QT). DS controls the number of branches of a tree dynamically. An improved performance of DS relative to QT is verified by analytical results and simulation studies.

Jitter is the variation of latencies, when real-time Intellectual Properties (IPs) are accessing data from the data storages. It is a critical factor for such IPs from the Quality-of-Service (QoS) perspective. Jitter of a real-time IP can be measured by how frequently it experiences the underflows and overflows from its data queue in read mode and write mode, respectively. Such failures critically depend on the bus arbitration scheme which determines the bus acquisition order of IPs. The proposed idea allows IPs to inform the bus arbiter of the status of their data buffers when they assert bus requests. Such information helps the bus arbiter to determine the bus acquisition order while greatly reducing the jitter. The experimental results show that our method effectively eliminates the overflows and underflows of real-time IPs by dynamically preempting the jitter-critical bus requests.

While efficient use of network resources is an important control objective of call admission control (CAC), the issue of fairness among services should also be taken into account. Game theory provides a suitable framework for formulating such fair and efficient CAC problem. Thus, in this paper, a game theoretic framework for selecting fair-efficient threshold parameters of CAC for the asymmetrical traffic case in CDMA mobile multimedia systems is proposed. For the cooperative game, the arbitration schemes for the interpersonal comparisons of utility and the bargaining problem, including the Nash, Raiffa, and modified Thomson solutions, are investigated. Furthermore, since CAC should be simple and flexible to provide a fast response to diverse QoS call requests during a connection setup, this paper also applies the concept of load factor to the previous Jeon and Jeong's CAC scheme and proposes an approximation approach to reduce the computational complexity (proposed throughput-based CAC scheme). From the numerical results, the proposed throughput-based CAC scheme shows a comparable performance to the previous Jeon and Jeong's CAC scheme while achieving lower computational complexity. All the solutions attain the fairness by satisfying their different fairness senses and efficiency by the Pareto optimality.

We propose a new output arbitration method for an input buffered switch with a buffered crossbar. In the proposed method, each output selects the first nonempty buffer from the starting point. The starting points of output are determined to minimize the synchronization phenomenon that more than one input module sends cells destined for a same output. Using an approximate analysis of the synchronization phenomenon, we show the uniqueness of the starting points improves the switch performance. Finally, using computer simulations, we verify the proposed method outperforms the previous methods under the uniform and burst traffic.

We propose a new input arbitration method for an input buffered switch with a buffered crossbar. In the proposed method, each input module selects the first eligible queue from the starting point. The starting points of input modules are different from each other in any case. We show that the uniqueness of the starting points improves the switch performance. Finally, using computer simulations, we confirm the proposed method is better than the conventional method under the uniform and on-off traffic.

A multi-QoS scalable-distributed-arbitration (MSDA) ATM switch is described that supports both high- and low-priority traffic under the head-of-line-priority discipline. It uses crosspoint and transit buffers, each consisting of a high- and low-priority buffer. The buffers arbitrate in a distributed manner the selection of which cellsto transmit. The MSDA switch supports multiple QoS classes while still providing the scalability of a previously described single-QoS scalable-distributed-arbitration (SSDA) switch. A problem occurs when the delay-time-based cell-selection mechanism used in the SSDA switch is applied to the low-priority traffic: it cannot achieve fairness in terms of throughput. This problem is overcome by introducing a distributed-ring-arbiter-based cell-selection mechanism at each crosspoint for the low-priority traffic. The low-priority transit buffer at each crosspoint has virtual queues, one for each upper input port. Cells for the low-priority traffic are selected by distributed-ring arbitration among the low-priority crosspoint buffer and these virtual queues. For the high-priority traffic, the same delay-time-based cell-selection mechanism is used as in the SSDA switch. Simulations show that the MSDA switch ensures fairness interms of delay time for the high-priority traffic and ensures fairness in terms of throughput for the low-priority traffic.

Input buffered switches most efficiently use memory and switch bandwidth. With Virtual Output Queueing (VOQ), head-of-line blocking can be avoided, thus breaking the throughput barrier of 58.6%. In this paper a switch architecture based on VOQ is proposed, which offers deterministic and stochastic delay bounds for prioritized traffic. This is achieved by a hybrid static and dynamic arbitration scheme, which matches ports both by a precalculated schedule and realtime calculations. By using weighted dynamic arbitration algorithms 100% throughput with lowest delays under all admissible traffic can be achieved. An integrated global priority scheme allows the multiplexing of realtime and data traffic. Following the arbitration decision, a cell scheduler decides locally in the input ports upon the next connection from which a cell is forwarded. Cell scheduling based on earliest-deadline-first (EDF) is shown to perform similar to its behaviour in an output-queued switch.

This paper proposes a high-speed crosspoint-buffer-type ATM switch, named Scalable-Distributed -Arbitration (SDA) switch. The SDA switch employs a new arbitration scheme that allows the switch to be scalable. The SDA switch has a crosspoint buffer and a transit buffer at every crosspoint. Arbitration is executed between the crosspoint buffer and the transit buffer. The arbitration selects a cell based on delay time using a synchronous counter. The selected cell is transferred from a crosspoint buffer to the output port by way of several transit buffers. Since arbitration is executed in a distributed manner at each crosspoint and the arbitration time does not depend on the switch size, the SDA switch can be expanded to realize large throughput. Numerical results show that the SDA switch ensures fairness in terms of delay time. In addition, the maximum delay time and the required crosspoint buffer size of the SDA switch are reduced, compared with those in the conventional switch based on ring arbitration. Thus, the proposed SDA switch based on the new arbitration scheme has a simple and expandable architecture,and will be suitable for future high-speed multimedia ATM networks.

This paper presents a high-fair bus arbiter for general multiprocessor systems. The arbiter realizes a new bus arbitration protocol which is a modification to the priority scheme specified in the group protocol enabling it to operate effectively on shared-bus multiprocessors to achieve fairness. The modified priority scheme not only guarantees that processors with low priority will gain access to the bus without being completely lock out as might happen during heavy traffic, but also assures that both bus waiting time and utilization on average of each processor closely approximate to other's. Hardware structure for the proposed protocol is also presented; the circuit is also capable of the feature of live insertion of processors from the system.

This letter describes the High-speed Statistical Retry switch (HSR switch) for high-speed ATM switching systems. The HSR switch uses a new matrix-shaped switching structure with buffers at input and ouptut ports, and a simple retry algorithm. The input buffers are very small, and no complicated arbitration function is employed. A cell is repeatedly transmitted from each input buffer at m times the input line speed until the input buffer receives an acknowledge signal from the intended output buffer. A maximum of one cell can be transmitted from each input buffer during the cell transmission time. The internal ratio (m) is decided according to the probability of cell conflict in the output line. Simulation results show that just a 10-cell buffer at each input port and a 50-cell buffer at each output port are required when m=4 to achieve a cell loss probability of better than 10-8, irrespective of the switch size. At each crosspoint, cells on the horizontal input line take precedence over those on the vertical input line. Only a very simple retry algorithm is employed, no complex arbitration is needed, and the arbitration circuit at the crosspoint can be reduced by about 90% in size. The proposed ATM switch architecture is applicable to high-speed (Gbit/s) ATM switches for B-ISDN because of its simplicity.