The selection of an appropriate key search algorithm for a specific application field is an important issue in application systems development. This is because data retrieval is the most time-consuming part of many application programs. An automatic selection method for key search algorithms is presented in this paper. The methodology has been implemented in a system called KESE2 (KEy-SEarch ALgorithm SElection). Key search algorithms are selected according to the user's requirements through interaction with KESE2 which bases its inferences on an evaluation table. This evaluation table contains values rating the performance of each key search algorithm for the different searching properties, or characteristics. The selection algorithm presented is based on step by step reduction of unsuitable key search algorithms and searching properties. The paper also proposes assistance facilities that consist of both a support function and a program synthesis function. Experimental results show that the appropriate key search algorithms are effectively selected, and that the necessary number of questions asked, to select the appropriate algorithm, is reduced to less than half of the total number of possible questions. The support function is useful for the user during the selection process and the program synthesis function fully translates a selected key search algorithm into high level language in an average of less than 1 hour.

A Hierarchical Cubic Network (HCN) is a hierarchical hypercube network proposed by Ghose. The HCN is topologically superior to many other similar networks, in particular, the hypercube. It has a considerably lower diameter than a comparable hypercube and is realized using almost half the number of links per node as a comparable hypercube. In this paper, we propose the shortest routing algorithm in HCN(n, n) and show that the diameter of HCN(n, n) with 22n nodes is n(n1)/31 which is about 2/3 of that of a comparable hypercube. We also propose the optimal routing algorithm in HCN(m, n) where mn and obtain that its diameter is n(m1)/31. Typical parallel algorithms run in HCN(m, n) with the same time complexity as a hypercube and the hypercube topology can be emulated with O(1) time complexity in it.

In this paper, we report a new approach about parsing and searching problem for a given phonetic lattice. The approach is based on the Divide and Conquer (DC) strategy. By dividing the phonetic lattice, we first construct a PD-tree to represent this lattice, then, we parse through this PD-tree to identify the possible sentence which is supposed to be the speech utterance. Next, we propose a new search scheme called Downward Request (DR) search model to decrease the computation costs, and this search model gives us the optimal or N-best solutions. Experiments performed on Chinese speech recognition show us the good results.

This paper describes the design of the reflective concurrent object-oriented specification language RMondel. RMondel is designed for the specification and modeling of distributed systems. It allows the development of executable specifications which may be modified dynamically. Reflection in RMondel is supported by two fundamental features that are: Structural Reflection (SR) and Behavioral Reflection (BR). Reflection is the capability to monitor and modify dynamically the structure and the behavior of the system. We show how the features of the language are enhanced using specific meta-operations and meta-objects, to allow for the dynamic modification of types (classes) and instances using the same language. RMondel specification can be modified by adding or modifying types and instances to get a new adapted specification. Consistency is checked dynamically at the type level as well as at the specification level. At the type level, structural and behavioral constrations are defined to preserve the conformance of types. At the specification level, a transaction mechanism and a locking protocol are defined to ensure the consistency of the whole specification.

The Manchester Dataflow Machine (MDFM) works with tasks of size equal to one single instruction. This fine granularity aims at exploring all parallelism at the instruction level. However, this project decision increases the instruction communication cost, which ends up to jam the interconnection network and reduces the system performance. One way to skirt this problem is to adopt variable size tasks instead of working with such small task size. In this paper, in order to study whether or not the usage of such variable size tasks in the MDFM architecture contributes to the improvement of the performance, some simulations by toy programs take place. In the simulation, variable size tasks are realized by packing the sequential instruction stretches into one task. To manage this packing, the Sequential Block (SB) technique is developed. The simulation of those packed and unpacked programs give an outline of advantages and disadvantages of working with variable size tasks, and how the SB technique should be implemented in the system.

A low power bus architecture with Local and Global Charge-Recycling Bus (Local-CRB and Global-CRB) techniques, featuring virtual stacking of the individual bus-capacitance and the dummy capacitor into a series configuration between supply voltage and ground, has been proposed. These Local and Global CRB schemes make it possible to reduce not only each bus-swing but also a total equivalent bus-capacitance of the ultra multi-bit buses running in parallel. The voltage swing of each bus is given by the recycled charge-supplying from the upper adjacent bus capacitance or the dummy capacitor, instead of the power line. The dramatical power reduction was verified by the simulated and measured data. According to these data, if employing the combination of those CRB schemes in a practical chip, the ultra-high data rate of 25 Gb/s can be achieved while maintaining the power dissipation to be less than 300 mW at Vcc3.6 V for the bus width of 512 bit with the bus-capacitance of 14 pF per bit operating at 50 MHz.

In this study we shall put forward a synergetic neural network and investigate the association dynamics. The present neuron model is substantially based on a top down formulation of the dynamic rule of an analog neural network in contrast to the conventional framework. It is proved that a complete association can be assured up to the same number of the embedded patterns as the number of neurons. In practice an association process is carried out for practical images with 256 gray scale levels and 256256 size. In addition, a searching process of the embedded patterns is also realised by means of controlling attraction parameters. Finally a stochastic model for the dynamic process is also proposed as an intermediate model between the association and the searching of the embedded patterns. Finally a stochastic property of the present model is characterized by fractal dimension of the excitation level of a neuron.

In this paper, we propose a hybrid hierarchical global router for multi-layer VLSI's, which executes routing and layering simultaneously. This novel approach, a hybrid hierarchical global router, is a combination of a topdown and a bottomup hierarchical routers, and may be one of interesting routing techniques. We also show experimental results, which demonstrate the superiority of the hybrid hierarchical approach. This approach may have many possibilities to be used in a various fields.

We have done a computer search for solutions of the equation x3y3z3n in the range max (|x|, |y|, |z|) 3414387 and 0 n 1000. We have discovered 21 new integer solutions for n {39, 143, 180, 231, 312, 321, 367, 439, 462, 516, 542, 556, 660, 663, 754, 777, 870}. As a result, there are 52 values of n (except n 4 (mod9)) for which no solutions are found.

For two finite disjoint sets P and Q of strings over an alphabet Σ, an alphabet indexing for P, Q by an indexing alphabet Γ with |Γ||Σ| is a mapping :ΣΓ satisfying (P)(Q), where :Σ*Γ* is the homomorphism derived from . We defined this notion through experiments of knowledge acquisition from amino acid sequences of proteins by learning algorithms. This paper analyzes the complexity of finding an alphabet indexing. We first show that the problem is NP-complete. Then we give a local search algorithm for this problem and show a result on PLS-completeness.

Processing elements (PEs) with a dynamically reconfigurable pipeline architecture allow the high-speed calculation of widely used neural model which is multi-layer perceptrons with the backpropagation (BP) learning rule. Its architecture that was proposed for a single chip is extended to multiprocessors' structure. Each PE holds an element of the synaptic weight matrix and the input vector. Multi-local buses, a swapping mechanism of the weight matrix and the input vector, and transfer commands between processor elements allow the implementation of neural networks larger than the physical PE array. Estimated peak performance by the measurement of single processor element is 21.2 MCPS in the evaluation phase and 8.0 MCUPS during the learning phase at a clock frequency of 50 MHz. In the model, multi-layer perceptrons with 768 neurons and 131072 synapses are trained by a BP learning rule. It corresponds to 1357 MCPS and 512 MCUPS with 64 processor elements and 32 neurons in each PE.

In the future satellite broadcasting system in 21GHz band, the rainfall attenuation is a most significant problem. To solve this problem, the hierarchical transmission systems have been studied. This paper analyzes the performance of the hierarchical modulation scheme from the view point of power assignment in the presence of the rainfall attenuation. This paper shows an optimum power assignment ratio to maximize the spectral efficiency and the signal-to-noise ratio of received image, and these optimum ratio is varied with the measure of system performance.

This paper describes an adaptively weighted code division multiplexing (AW-CDM) system, in other words, power controlled spread-spectrum multiplexing system and describes its application to hierarchical digital broadcasting of television signals. The AW-CDM, being combined with multi-resolutional video encoder, can provide such a hierarchical transmission that allows both high quality services for fixed receivers and reduced quality services for mobile/portable receivers. The carrier and the clock are robustly regenerated by using a spread-spectrum multiplexed pseudorandom noise (PN) sounder as a reference in the receiver. The PN reference is also used for Rake combining with signals via different paths, and for adaptive equalization (EQ). In a prototype AW-CDM modem, three layers of hierarchical video signals (highs: 5.91Mbps, middles: 1.50Mbps, and lows: 0.46 Mbps) are divided into a pair of 64 orthogonal spread-spectrum subchannels, each of which can be given a different priority and therefore a different threshold. In this case, three different thresholds are given. The modem's transmission rate is 9.7Mbps in the 6MHz band. Indoor transmission tests confirm that lows (weighted power layer I), middles (averaged power layer II), and highs (lightened power layer III) are retrievable under conditions in which the desired to undesired signal ratios (DURs) are respectively 0dB, 8.5dB, and 13.5dB. If the undesired signals are multipaths, these performances are dramatically improved by Rake combining and EQ. The AW-CDM system can be used for 20-30 Mbps advanced television (ATV) transmission in the 6-MHz bandwidth simply by changing the binary inputs into quaternary or octonary inputs.

Video compression technologies such as MPEG have enabled the efficient use of video data in the computer environment. However, the compressed video information still has a huge amount of data compared with the other media such as text, audio, and graphics. Therefore, it is very important to handle the video information in a networked database for the efficient use of resources like storage media. Furthermore, in the networked database, its retrieval methods including search and delivery become the key issues especially for the video information which requires a large network bandwidth. In this paper, a video browsing method using an automatic fast scene cut detection for networked video database access is described. The scene cut is defined as the scene change frame and is detected by temporal change in interframe luminance difference and chrominance correlation which are obtained from spatio-temporally scaled image directly extracted from the MPEG compressed video without any complex processing of video decoding. The detected scene change frames are further investigated to exploit the relationship between the scene cuts and are classified in order to make a hierarchical indexing. These results of detection are stored as an scene index file using the MPEG format. The simulation results are also presented for several test video sequences to show that these methods have enabled the efficient video database construction and accessing.

There are two approaches to implementing the international standard video coding algorithms such as H.261 and MPEG: a programmable DSP approach and a building block approach. The advantages and disadvantages of each are discussed here in detail, and the video coding algorithms and required throughput are also summarized. For more complex standard such as MPEG-, VLSI architecuture became more sophisticated. The DSP approach incorporates special processing engines and the building block approach integrates general-purpose microprocessors. Both approaches are capable of MPEG- NTSC coding in a single chip. Reduction of power consumption is a key issue for video LSIs. Architectures and circuits that reduce the supply voltage while maintaining throughput are summarized. A 0.25-µm, 3-GOPS, 0.5-W, SIMD-VSP for portable MPEG- systems could be made by using architecture-driven voltage scaling as well as feature-size scaling and SOI devices.

This paper proposes new real–time heuristic distributed parallel algorithms for search, which are based on the concepts of propagations and competitions of concurrent waves. These algorithms are characterized by simplicity and clearness of control strategies for search, and distinguished abilities in many aspects, such as real–time performance, wide suitability for searching AND/OR implicit graphs, and ease in hardware implementation.

In general, message passing multiprocessors suffer from communication overhead and shared memory multiprocessors suffer from memory contention. Also, data I/O overhead limits performance. In particular, computer vision tasks that require massive computation are strongly affected by these disadvantages. This paper proposes new parallel architectures for computer vision, a Flexibly (Tightly/Loosely) Coupled Multiprocessor (FCM) and a Flexibly Coupled Hypercube Multiprocessor (FCHM) to alleviate these problems. FCM and FCHM have a variable address space memory in which a set of neighboring memory modules can be merged into a shared memory by a dynamically partitionable topology. FCM and FCHM are based on two different topologies: reconfigurable bus and hypercube. The proposed architectures are quantitatively analyzed using computational models and parallel vision algorithms are simulated on FCM and FCHM using the Intel's Personal SuperComputer (iPSC), a hypercube multiprocessor, showing significant performance improvements over that of iPSC.

There has been an increasing demand for telecommunication services that satisfy individual users' requirements such as personal telecommunication services and intelligent network services. This demand for advanced telecommunications services is having a great impact on the control architecture and mechanism. In this paper, we propose a new representation of processing power for telecommunications services, using TPS (Transaction Per Second), instead of BHCA, which has been the most commonly used parameter for conventional telephone networks. In developing an IN benchmark, telecommunications services are compared with the TPC-A (Transaction Processing Performance Council-A) benchmark model based on TPS. This benchmark is then used to estimate the requirements for processing power, which, in turn, indicate the necessity for a distributed control. A layered architecture, compatible architecture, and control mechanism for user services are employed to adapt to the distributed network environment.

By addressing design requirements for multicast ATM switching, this paper attempts to provide an integrated view of modular and expandable switch architectures suitable for both unicast and multicast switching for future B-ISDNs. Several large and modular multicast ATM switching architectures are discussed, each of which handles different traffic situations. These architectures consist of multiple shared-buffer copy network modules of adequate size suitable for fabrication on a single chip, and small output memory switch modules. A new modular link-grouped multistage interconnection network is proposed for interconnecting copy network modules and memory switch modules, so that future large multicast ATM switching networks can be built in a modular fashion. The described modular architectures can significantly facilitate signal synchronization in large-scale switching networks.

Multimedia services based on broadband ISDN (B-ISDN) technology need a network architecture that satisfies the requirements of users, carriers, and vendors. This paper describes a new network architecture for B-ISDN service control and management based on INA. We list general requirements, and present implementation issues of INA. A network architecture and main components, which resolve implementation issues, is then proposed. We also describe a video-on-demand service based on our proposed architecture.