The authors have studied mechanism of transition from metallic phase to gaseous phase in contact break arc. For further elucidation of the mechanism, we have carried out spectroscopic measurement. The spectrum measurement system which had high time resolution was composed using two monochromators and a bifurcated image fiber, which had one input port and two output ports. The input port received the arc light, and the two monochromators received the arc light from the two output ports, respectively. The spectral sensitivity of the two monochromators was corrected with a standard lamp. We have measured simultaneously two spectra of break arc for Ag in laboratory air, under the condition where source voltage E=48 V, load inductance L=2.3 mH, and closed contact current I0=6 A. As a result, the time-varying tendency of spectrum intensity is similar for the same element, even if the wavelength is different. And from the comparison of time average spectrum intensity, it is clarified that average intensity for gas spectrum does not attain to 10% of that for metallic atomic spectrum (Ag I, 520.91 nm). In addition, the decrease point of Ag II (ion) spectrum has been found to correspond with the peak of Ag I (atom) spectrum.

Arc discharge between electrodes of relays and switches often causes contact surface damage through material transfer and arc erosion. Especially, material transfer sometimes occurs and brings serious failure even under lower load that is quite smaller than the minimum arc current value of contact material. In this paper, contact surface configuration, material transfer, and arc erosion characteristics of Ag and AgPd 60 contacts were experimentally studied after 0.5 or 1 million switching operations at various load levels. The followings can be made clear. Firstly, it was confirmed that the arcs and material transfer occurred even under such current that was lower than the minimum arc current. Therefore, the definition of the arc occurrence boundary current was newly determined. Secondly, the relation between load conditions (current and power supply voltage) and contact surface configuration (craters and pips) caused by material transfer was studied. The arc erosion behaviors of tested samples could be classified into two types: material transfer type and wear-out type. As one of the primary factors of transition from the former type to the latter one, contact activation was considered. The influences of load conditions and organic gas emitted from relay structure on arc characteristics was experimentally examined. The results indicated that load current greatly influenced the amount of material transfer and that power supply voltage affected the occurrence of the wear-out type significantly. The activation behavior of the contact surface could be found through observing the bridge voltage waveform.

The prediction of a relay contact's life is still very important for support and maintenance of the Crossbar Switching Systems. It was found through surveys and experiments that the protected shower arc is the main reason for switching-relay contact erosion at existing Crossbar Switching Systems, if the contacts were not heavily activated. If the contacts were heavily activated, a long sustained steady arc might occur and severely erode the contacts. This paper proposes an arch energy estimation method for the prediction of contact erosion using object-oriented simulation technology when a steady arc occurs at protected contacts. The arc energy is expressed in a simulation model through analysis, and the model was confirmed through experimentation. The simulation model was used for building block programs of an expert system to predict the life span of switching relays in the existing Crossbar Switching Systems.

This paper describes a simple system of measuring the spatial distributions of spectral intensities with AgI-421 nm and AgI-546 nm among many optical spectrums emitted from an arc discharge between separating Ag contacts. In order to detect the intensities of two optical spectrums, the prototype equipment has two sets assembled with a CCD color linear image sensor, a lens and optical filters, which are arranged on rectangularity. The intensities of two spectrums can be recorded with 2 ms time-resolution within a long arc duration on a digital memory. The recorded digital signals are processed by using a personal computer in order to reconstruct two spatial distributions of spectral intensities in a cross section of arc column with the Algebraic Reconstruction Technique.

The former experimental results have already shown that it is oxide films formed on contact surface causing the contact resistance to degrade in dc. breaking arcs for Ag and Pd materials. In order to understand the detailed information about it, the experiments are performed to break dc. inductive load at 20 V, 0.5 A and 1.0 A in nitrogen gas with different oxygen concentrations. The contact surface morphology and surface contamination are evaluated by SEM and AES, respectively. The tested results demonstrate that, for Ag contact, the severe oxidation occurs with increasing oxygen concentration, and the critical value of oxygen concentration is found to be about 10% and 5% in 0.5 A and 1.0 A, respectively, above those values the contact resistance degrades due to the oxide films formed on the contact surface, especially on the anode surface. While, for Pd contacts, a remarkable contact resistance degradation is not found even at 1.0 A in oxigen. Evidence shows that the arc duration, in particular the gaseous phase arc duration affects the anode oxidation, which in turn causes the significant fluctuation of contact resistance.

Reliability of an electric contact can be defined by two parameters, contact resistance and wear, and the parameters of contacts operated in arcing condition are governed by the arc discharge. Thus the measurement on the relationship between the parameters and arc phenomena is necessary to improve the contact performance. The parameters for arcing electric contacts and problems were reviewed, and new concept for electric contact testing systems was proposed. Measurement with such an advanced system should be concurrent parallel measurement, quantitative measurement of degradation, systematic measurement, and analysis of arc discharge phenomena. Some examples of advanced measurement systems and new data obtained with such systems were described. Systematic results on relationships between condition and performance parameters were obtained by systematic measurement with systematically settled conditions, such as opening speed or material condition. A measurement method for the metallic phase arc duration was developed by the authors, and role of the metallic phase arc on contact performance parameters was found from interpretation of obtained data. The real-time surface profile measurement of an operating contact and the optical transient spectrum analyser for arc light radiated from breaking contact were also described.

Recent achievements in low-voltage and low-power circuit techniques are reported in this paper. DC current in low-voltage CMOS circuits stemming from the subthreshold current in MOS transistors, is effectively reduced by applying switched-power-line schemes. The AC current charging the capacitance in DRAM memory arrays is reduced by a partial activation of array blocks during the active mode and by a charge recycle during the refresh mode. A very-low-power reference-voltage generator is also reported to control the internal chip voltage precisely. These techniques will open the way to using giga-scale LSIs in battery-operated portable equipment.

The newly developed high speed DRAMs are introduced and their innovative circuit techniques for achieving a high data bandwidth are described; the synchronous DRAM, the cache DRAM and the Rambus DRAM. They are all designed to fill the performance gap between MPUs and the main memory of computer systems, which will diverge in '90s. Although these high speed DRAMs have the same purpose to increase the data bandwidth, their approaches to accomplish it is different, which may in turn lead to some advantages or disadvantages as well as their fields of applications. The paper is intended not only to discuss them from technical overview, but also to be a guide to DRAM users when choosing the best fitting one for their systems.

Linear lightwave networks (LLNs) are optical networks in which network nodes perform only linear operations on optical signals: power splitting, combining, and non-regenerative amplification. While previous efforts on LLNs assume only one fiber per link, we consider a multi-fiber linear lightwave network (M-LLN) architecture for telecommunications where switching exchanges are normally connected by multi-fiber cables. We propose a class of linear path (LP) allocation schemes for establishing optical paths in M-LLNs, and show that they have a better performance than those proposed for single-fiber LLNs. We show that M-LLNs can be implemented with commercially available components, and discuss the implementation issues in detail.

The paper describes the architecture and the simulated performances of a memory-based chip that emulates human cortical processing in early visual tasks, such as texture segregation. The featural elements present in an image are extracted by a convolution block and subsequently processed by the cortical chip, whose neurons, organized into three layers, gain relational descriptions (intelligent processing) through recurrent inhibitory/excitatory interactions between both inter-and intra-layer parallel pathways. The digital implementation of this architecuture directly maps the set of equations determining the status of the cortical network to achieve an optimal exploitation of VLSI technology in neural computation. Neurons are mapped into a memory matrix whose elements are updated through a programmable computational unit that implements synaptic interconnections. By using 0.5 µm-CMOS technology, full cortical image processing can be attained on a single chip (2020 mm2 die) at a rate higher than 70 frames/second, for images of 256256 pixels.

An automatic zip code recognition system for Japanese mail is proposed in this paper. It is assumed that a zip code is composed of three numerals and requited to be written in a specified frame. In actual images, however, the three numerals sometimes extend outside the specified frame and are not clearly separated. Considering this situation, the authors devised a system with two stages, the segmentation stage and the recognition stage. The segmentation stage consists of five steps: setting and adjusting of initial areas for numeral images (figures), calculation of the center of gravity of each figure, search for the horizontal and vertical boundaries of each figure, determination of the final area for each figure, and normalization of the figure in each final area. In the recognition stage, the Localized Arc Pattern Method (Arc method) proposed by Yoshimura et al. (1991) is implemented hierarchically; that is, a simple Arc method is applied first to each figure and a more complex one is applied subsequently unless the figure is identified in the first step. In the recognition process, every figure is judged as a numeral or otherwise rejected. The proposed system was applied to a database provided by the Institute for Post and Telecommunications Policy (IPTP). The segmentation algorithm yielded an adequate result. The recognition algorithm yielded scores as high as 90.6% in correct recognition rate and 0.7% in error rate. The best score of the precision index (P-index) specified by the IPTP was as low as 15.7 for the above mentioned IPTP database, while the score for another IPTP database was 16.9.

This paper presents a new line extraction method to capture vectors based on contours and skeletons from line drawing raster images in which the lines are touched by characters or other lines. Conventionally, two line extraction methods have generally been used. One is a thinning method. The other is a medial line extraction method based on parallel pairs of contours. The thinning method tends to distort the extracted lines, especially at intersections and corners. On the other hand, the medial line extraction method has a poor capability as regards capturing correct lines at intersections. Contours are able to maintain edge shapes well, while skeletons preserve topological features; thus, a combination of these features effectively leads to the best fitting line. In the proposed method, the line which best fits the original image is selected from among various candidate lines. The candidates are created from several merged short skeleton fragments located between pairs of short contour fragments. The method is also extended to circular arc fitting. Experimental results show that the proposed line fitting method is effective.

This paper presents an algorithm for string searching in a character lattice. A character lattice, which is obtained through a character recognition process, is a general and flexible data structure that represents many hypothesized strings in a document image. In this paper, the authors propose a simple and efficient algorithm; it consists of a single loop of some set-operations and scans the character lattice only once. The authors also describe two actual implementations of the algorithm; one uses Bit-Arrays and the other a Trie. Owing to its bir parallelism, the Bit-Array approach is able to search for a single pattern faster than the Trie approach, and is easily extended to complex matchings such as an approximate one. It is suited for document retrieval systems that need to search for a keyword as fast as possible. A hashed compact version of the character lattice is also useful to increase the speed of the search for a single pattern. In contrast, the Trie approach is able to search for a large number of patterns simultaneously, and is suited for document understanding systems that need to extract words from the character lattice. The experimental results have shown that both approaches achieve high performance.

Persistent data structures, introduced by Sarnak and Tarjan, have been found especially useful in designing geometric algorithms. In this paper, we present a persistent form of binary-binary search tree, and then apply this data structure to solve various geometric searching problems, such as, three dimensional ray-shooting, hidden surface removal, polygonal point enclosure searching and so on. In all applications, we are able to either improve existing bounds or establish new bounds.

This paper introduces a new class of machines called multihead marker finite automata, and investigates how the number of markers affects its accepting power. Let HM{0}(i, j)(NHM{0}(i, j))denote the class of languages over a one-letter alphabet accepted by two-way deterministic (nondeterminstic) i-head finite automata with j markers. We show that HM{0} (i, j) HM{0}(i, j1) and NHM{0}(i, j) NHM{0}(i, j+1) for each i2, j0.

The paper studies a high-ranking node in a broadband integrated services digital network(B-ISDN). The input traffic is classified into two types: real-time and non-real-time. For each type of input traffic, we assume that the message arrival process is a batch Poisson process and that the message size is arbitrarily distributed so as to describe services from narrowband to wideband. We model the high-ranking node by a queueing system with multiple synchronous servers and two separate finite buffers, one for each type of traffic. We derive performance measures exactly by using a two-dimensional imbedded discrete-time Markov chain analysis, within which the transition probabilities are obtained via an application of the residue theorem in complex variables. The performance measures include the blocking probability, delay, and throughput.

It is recognized in Japan that reformation of the national research institutions is urgently necessary. Present situation and constraints are shown and the action items are discussed.

This paper describes a vision system, which is based on ASIC (Application Specific Integrated Circuit) approaches, for vehicle guidance on highways. After reviewing related work in the field of intelligent vehicles, stereo vision, and ASIC-based approaches, the paper focuses on a stereo vision system developed for intelligent cruise control. The system measures the distance to the vehicle in front using trinocular triangulation. Application specific processor architectures were developed for low mass-production cost, real-time operation, low power consumption, and small physical size. The system was installed in a trunk of a car and evaluated successfully on highways.

Space-time tradeoff is a very fundamental issue to design a fault-tolerant real-time (called responsive) system. Routing a message in large computer networks is efficient when each node knows the full topology of the whole network. However, in the hierarchical routing schemes, no node knows the full topology. In this paper, a tradeoff between an optimality of path length (message delay: time) and the amount of topology information (routing table size: space) in each node is presented. The schemes to be analyzed include K-scheme (by Kamoun and Kleinrock), G-scheme (by Garcia and Shacham), and I-scheme (by authors). The analysis is performed by simulation experiments. The results show that, with respect to average path length, I-scheme is superior to both K-scheme and G-scheme, and that K-scheme is better than G-scheme. Additionally, an average path length in I-scheme is about 20% longer than the optimal path length. On the other hand, for the routing table size, three schemes are ranked in reverse direction. However, with respect to the order of size of routing table, the schemes have the same complexity O (log n) where n is the number of nodes in a network.

Multiplication-accumulation is the basic computation required for image filtering operations. For real-time image filtering, very high throughput computation is essential. This work proposes a hardware algorithm for an application-specific VLSI architecture which realizes an area-efficient high throughput multiplier-accumulator. The proposed algorithm utilizes a priori knowledge of filter mask coefficients and optimizes number of basic hardware components (e.g., full adders, pipeline latches, etc.). This results in the minimum area VLSI architecture under certain input/output constraints.