The following, which is related to the design of the microwave filters, is mainly presented: (1) certain useful approximation which can be obtained by double-resistive- terminated 2-ports consisting of a cascade of two 1-variable 2-ports in different variables, and (2) an approach for filter design from 2-variable viewpoint. Approximations presented provide useful magnitude responses in 2-D domain. Hence it is discussed that how the provided 2-D responses can be used for the design of the microwave filters. Furthermore, properties of the 2-variable transfer functions resulting in such circuits are given.

In this paper, a threshold voltage (VT) cancellation circuit for neuron-MOS (νMOS) analog circuits is described. By connecting the output terminal of this circuit with one of the input terminals of the νMOS transistor, cancellation ofVT is realized. The circuit has advantages of ground-referenced output and is insensitive to the fluctuation of bias and supply voltages. Second-order effects, such as the channel length modulation effect, the mobility reduction effect and device mismatch of the proposed circuit are analyzed in detail. Low-power and high-swing νMOS cascode current mirror is presented as an application. Performance of the proposed circuits is confirmed by HSPICE simulation with MOSIS 2. 0 µ p-well double-poly and double-metal CMOS device parameters.

This paper describes an N-type and a P-type MOS cascode circuit based on the square-law characteristics of an MOS transistor in saturation region. The transconductance parameter ratios of an upper and a lower MOS transistor are set to be 1: n2 for the N-type MOS cascode circuit and n2: 1 for the P-type MOS cascode circuit. The N and P-type MOS cascode circuits are divided to four types by the difference of connections of input terminals. We consider the input-output relations of each type circuit. The second-order effects of the circuit such as channel length modulation effect, mobility reduction effect and device mismatch are analyzed. As applications, an analog voltage adder and a VT level shifter using MOS cascode circuits are presented. All of the proposed circuits are very simple and consist of only the N and P-type MOS cascode circuits. The proposed circuits aer confirmed by SPICE simulation with MOSIS 1.2µm CMOS process parameters.

A new CMOS analogue transconductor is proposed and simulated. This transconductor is based on the operation of MOS transistors in the linear region and has a good linearity. The simulation result shows that less than 1% distortion can be obtained for the differential input signal of 6.4 Vp-p with IB=80µA and supply voltage of 5V.

This paper describes a novel input-free MOS VT extractor circuit. The circuit consists of a bias voltage block and a novel VT extractor block. The proposed VT extractor block has the advantages of the ground-referenced output, low influence of the nonideality, few numbers of transistors and no influence of the PMOS process. The PSpice simulations show the supply voltage range and the bias voltage range of the proposed circuit are wider than those of Johnson's or Wang's.

This paper proposes a constructive linearization method for transistor circuits based on a polynomial representation of nonlinear transfer functions. The nonlinear transfer functions for various configurations have been shown in a polynomial form. Then the results have been applied to several bipolar transistor circuits to exemplify the proposed designing method.

Two types of novel nVT level shift circuits based on the square law characteristics of MOSFETs have been proposed. These circuits generate VIN+nVT or VIN-nVT (where VT is a threshold voltage), if the input voltage is applied as the VIN. These circuits can be widely used in MOSFET characterization, compensating VT effect, VT measurement, level shifting, etc. Type 1 is directly derived from the nVT-sift circuit proposed by Wang. Type 2 can reduce a total chip area than type 1 and has a wider input range. SPICE simulations show that the proposed circuits have a very wide input range and a small power consumption.

OTA (Operational Transconductance Amplifier) is a useful circuit in analog signal processing systems, especially in high-frequency applications. Important features of OTA are: infinite input impedance, electrically changeable transconductance (Gm), and much wider operation range without negative feedback such as in OPamp applications. The good linearity of OTA over wide input range is necessary to extend the application fields of OTA. Several techniques are developed to extend the input range with good linearity. In this paper, a highly-linear CMOS-OTA operating under 1 V power supply, is proposed. The concept of the proposed OTA is based on class-AB operation of two n-channel MOSFETs in the saturation region. By improving the input stage circuits, wide input range can be achieved. SPICE simulations are performed to verify the performance of the proposed OTA.