In this paper we extend hyperparameter-free sparse signal reconstruction approaches to permit the high-resolution time delay estimation of spread spectrum signals and demonstrate their feasibility in terms of both performance and computation complexity by applying them to the ISO/IEC 24730-2.1 real-time locating system (RTLS). Numerical examples show that the sparse asymptotic minimum variance (SAMV) approach outperforms other sparse algorithms and multiple signal classification (MUSIC) regardless of the signal correlation, especially in the case where the incoming signals are closely spaced within a Rayleigh resolution limit. The performance difference among the hyperparameter-free approaches decreases significantly as the signals become more widely separated. SAMV is sometimes strongly influenced by the noise correlation, but the degrading effect of the correlated noise can be mitigated through the noise-whitening process. The computation complexity of SAMV can be feasible for practical system use by setting the power update threshold and the grid size properly, and/or via parallel implementations.

Timing vernier (i.e., digital-to-time converter) is a key component of the pin-electronics circuit board installed in automated digital-VLSI test equipment, and it is used to create fine delays of less than one-cycle time of a clock signal. This paper presents a new on-the-fly (timing-) jitter suppression technique which makes it possible to use low-power plain-CMOS-logic-based timing verniers. Using a power-compensation line installed at the poststage of the digitally variable delay line, we make every pulse (used as a timing signal) consume a fixed amount of electric energy independent of the required delay amount. Since the power load of intrapowerlines is kept constantly, the jitter increase in the situation of changing the required delay amount on the fly is suppressed. On the basis of the concept, a 10-ns span, 125-MHz timing-vernier macro was designed and fabricated with a CMOS process for logic VLSIs. Every macro installed in a real-time timing-signal generator VLSI achieved the required timing resolution of 31.25ps with a linearity error within 15ps. The on-the-fly jitter was successfully suppressed to a random jitter level (<26ps p-p).

High frame rate and ultra-low delay matching system plays an increasingly important role in human-machine interactive applications which call for higher frame rate and lower delay for a better experience. The large amount of processing data and the complex computation in a local feature based matching system, make it difficult to achieve a high process speed and ultra-low delay matching with limited resource. Aiming at a matching system with the process speed of more than 1000 fps and with the delay of less than 1 ms/frame, this paper puts forward a local binary feature based matching system with field-programmable gate array (FPGA). Pixel selection based 4-1-4 parallel matching and intensity directed symmetry are proposed for the implementation of this system. To design a basic framework with the high process speed and ultra-low delay using limited resource, pixel selection based 4-1-4 parallel matching is proposed, which makes it possible to use only one-thread resource consumption to achieve a four-thread processing. Assumes that the orientation of the keypoint will bisect the patch best and will point to the region with high intensity, intensity directed symmetry is proposed to calculate the keypoint orientation in a hardware friendly way, which is an important part for a rotation-robust matching system. Software experiment result shows that the proposed keypoint orientation calculation method achieves almost the same performance with the state-of-art intensity centroid orientation calculation method in a matching system. Hardware experiment result shows that the designed image process core supports to process VGA (640×480) videos at a process speed of 1306 fps and with a delay of 0.8083 ms/frame.

This paper aims to establish expressions for IEEE 802.11 string-topology multi-hop networks with transmission control protocol (TCP) traffic flow. The relationship between the throughput and transport-layer function in string-topology multi-hop network is investigated. From the investigations, we obtain an analysis policy that the TCP throughput under the TCP functions is obtained by deriving the throughput of the network with simplified into two asymmetric user datagram protocol flows. To express the asymmetry, analytical expressions in medium access control-, network-, and transport layers are obtained based on the airtime expression. The expressions of the network layer and those of transport layer are linked using the “delayed ACK constraint,” which is a new concept for TCP analysis. The analytical predictions agree well with the simulation results, which prove the validity of the obtained analytical expressions and the analysis policy in this paper.

This study proposes a maximum-likelihood-estimation method for a quadrotor UAV given the existence of sensor delays. The state equation of the UAV is nonlinear, and thus, we propose an approximated method that consists of two steps. The first step estimates the past state based on the delayed output through an extended Kalman filter. The second step involves calculating an estimate of the present state by simulating the original system from the past to the present. It is proven that the proposed method provides an approximated maximum-likelihood-estimation. The effectiveness of the estimator is verified by performing experiments.

Software-defined networking (SDN) has emerged as a promising approach to enable network innovation, which can provide network virtualization through a hypervisor plane to share the same cloud datacenter network among multiple virtual networks. While, this attractive approach may bring some new problem that leads to more susceptible to the failure of network component because of the separated control and forwarding planes. The centralized control and virtual network sharing the same physical network are becoming fragile and prone to failure if the topology of virtual network and the control path is not properly designed. Thus, how to map virtual network into physical datacenter network in virtualized SDN while guaranteeing the survivability against the failure of physical component is extremely important and should fully consider more influence factors on the survivability of virtual network. In this paper, combining VN with SDN, a topology-aware survivable virtual network embedding approach is proposed to improve the survivability of virtual network by an enhanced virtual controller embedding strategy to optimize the placement selection of virtual network without using any backup resources. The strategy explicitly takes account of the network delay and the number of disjoint path between virtual controller and virtual switch to minimize the expected percentage of control path loss with survivable factor. Extensive experimental evaluations have been conducted and the results verify that the proposed technology has improved the survivability and network delay while keeping the other within reasonable bounds.

As application hardware designs and implementations in a short term are required, high-level synthesis is more and more essential EDA technique nowadays. In deep-submicron era, interconnection delays are not negligible even in high-level synthesis thus distributed-register and -controller architectures (DR architectures) have been proposed in order to cope with this problem. It is also profitable to take data-bitwidth into account in high-level synthesis. In this paper, we propose a bitwidth-aware high-level synthesis algorithm using operation chainings targeting Tiled-DR architectures. Our proposed algorithm optimizes bitwidths of functional units and utilizes the vacant tiles by adding some extra functional units to realize effective operation chainings to generate high performance circuits without increasing the total area. Experimental results show that our proposed algorithm reduces the overall latency by up to 47% compared to the conventional approach without area overheads by eliminating unnecessary bitwidths and adding efficient extra FUs for Tiled-DR architectures.

Small delay caused by a resistive open is difficult to test since circuit delay varies depending on various factors such as process variations and crosstalk even in fault-free circuits. We consider the problem of discriminating a resistive open by anomaly detection using delay distributions obtained by the effect of various input signals provided to adjacent lines. We examined the circuit delay in a fault-free circuit and a faulty circuit by applying electromagnetic simulator and circuit simulator for a line structure with adjacent lines under consideration of process variations. The effectiveness of the method that discriminates a resistive open is shown for the results obtained by the simulation.

Three-dimensional integrated circuits (3D ICs) that employ through-silicon vias (TSVs) integrating multiple dies vertically have opened up the potential of highly improved circuit designs. However, various types of TSV defects may occur during the assembly process, especially the clustered TSV faults because of the winding level of thinned wafer, the surface roughness and cleanness of silicon dies,inducing TSV yield reduction greatly. To tackle this fault clustering problem, router-based and ring-based TSV redundancy architectures were previously proposed. However, these schemes either require too much area overhead or have limited reparability to tolerant clustered TSV faults. Furthermore, the repairing lengths of these schemes are too long to be ignored, leading to additional delay overhead, which may cause timing violation. In this paper, we propose a region-based TSV redundancy design to achieve relatively high reparability as well as low additional delay overhead. Simulation results show that for a given number of TSVs (8*8) and TSV failure rate (1%), our design achieves 11.27% and 20.79% reduction of delay overhead as compared with router-based design and ring-based scheme, respectively. In addition, the reparability of our proposed scheme is much better than ring-based design by 30.84%, while it is close to that of the router-based scheme. More importantly, the overall TSV yield of our design achieves 99.88%, which is slightly higher than that of both router-based method (99.53%) and ring-based design (99.00%).

Delay Tolerant Networks (DTN) protocols based on the store-and-carry principle offer useful functions such as forwarding, utility value, social networks, and network coding. Although many DTN protocol proposals have been offered, work continues to improve performance. In order to implement DTN functions, each protocol introduces multiple parameters; their performance is largely dependent on how the parameter values are set. In this paper, we focus on improving spray and wait (S&W) by proposing a communication protocol named a Spray and AHP-GRA-based Forwarding (S&AGF) and Spray and Fuzzy based Forwarding (S&FF) scheme for DTN. The proposed protocols include a new forwarding scheme intended to extend network lifetime as well as maintain acceptable delivery ratio by addressing a deficiency in existing schemes that do not take energy into consideration. We choose the most suitable relay node by taking the energy, mobility, measured parameters of nodes into account. The simulation-based comparison demonstrates that the proposed S&AGF and S&FF schemes show better balanced performance level in terms of both delivery ratio and network lifetime than original S&W and its variants.

Recently, P2PTV is a popular application to deliver video streaming data over the Internet. On the overlay network, P2PTV applications create logical links between pairs of peers considering round trip time (RTT) without physical network consideration. P2PTV packets are shared over a network without localization awareness which is a serious problem for Internet Service Providers (ISPs). A delay-insertion-based traffic localization scheme was proposed for solving this problem. However, this scheme sometimes leads the newly joining peer to download streaming traffic from a local neighbor peer which has only scarce upload bandwidth. This paper proposes a novel scheme of delay-insertion-based traffic localization in which the router estimates relay capability to each relay peer candidate and leads the newly joining peer to connect to a neighbor peer with sufficient performance for relaying video data. Parameters were evaluated for the optimized condition in the relay capability estimation process. In addition, experiments conducted on a real network show that our proposed scheme can prevent the newly joining peer from downloading video data from peers with insufficient relay capability and maintain video quality close to normal in a P2PTV system while ensuring efficient traffic localization at the level of the Autonomous System (AS) network.

This paper introduces distributed array antenna (DAA) systems that offer high antenna gain. A DAA consists of several small antennas with improved antenna gain. This paper proposes a technique that suppresses the off-axis undesired radiation and compensates the time delay by combining signal processing with optimization of array element positioning. It suppresses the undesired radiation by compensating the delay timing with high accuracy and deliberately generating the inter-symbol interference (ISI) in side-lobe directions. Computer simulations show its effective suppression of the equivalent isotropic radiated power (EIRP) pattern and its excellent BER performance.

For network researchers and practitioners, active measurement, in which probe packets are injected into a network, is a powerful tool to measure end-to-end delay. It is, however, suffers the intrusiveness problem, where the load of the probe traffic itself affects the network QoS. In this paper, we first demonstrate that there exists a fundamental accuracy bound of the conventional active measurement of delay. Second, to transcend that bound, we propose INTrusiveness-aware ESTimation (INTEST), an approach that compensates for the delays produced by probe packets in wired networks. Simulations of M/M/1 and MMPP/M/1 show that INTEST enables a more accurate estimation of end-to-end delay than conventional methods. Furthermore, we extend INTEST for multi-hop networks by using timestamps or multi-flow probes.

In this paper, we propose a floorplan aware high-level synthesis algorithm with body biasing for delay variation compensation, which minimizes the average leakage energy of manufactured chips. In order to realize floorplan-aware high-level synthesis, we utilize huddle-based distributed register architecture (HDR architecture). HDR architecture divides the chip area into small partitions called a huddle and we can control a body bias voltage for every huddle. During high-level synthesis, we iteratively obtain expected leakage energy for every huddle when applying a body bias voltage. A huddle with smaller expected leakage energy contributes to reducing expected leakage energy of the entire circuit more but can increase the latency. We assign control-data flow graph (CDFG) nodes in non-critical paths to the huddles with larger expected leakage energy and those in critical paths to the huddles with smaller expected leakage energy. We expect to minimize the entire leakage energy in a manufactured chip without increasing its latency. Experimental results show that our algorithm reduces the average leakage energy by up to 39.7% without latency and yield degradation compared with typical-case design with body biasing.

Linear phase maximally flat digital differentiators (DDs) with stopbands obtained by minimizing the Lp norm are filters with important practical applications, as they can differentiate input signals without distortion. Stopbands designed by minimizing the Lp norm can be used to control the relationship between the steepness in the transition band and the ripple scale. However, linear phase DDs are unsuitable for real-time processing because each group delay is half of the filter order. In this paper, we proposed a design method for a low-delay maximally flat low-pass/band-pass FIR DDs with stopbands obtained by minimizing the Lp norm. The proposed DDs have low-delay characteristics that approximate the linear phase characteristics only in the passband. The proposed transfer function is composed of two functions, one with flat characteristics in the passband and one that ensures the transfer function has Lp approximated characteristics in the stopband. In the optimization of the latter function, Newton's method is employed.

This paper proposes an effective continuous super-resolution (CSR) algorithm for the multipath channel estimation. By designing a preamble including up-chirp and down-chirp symbols, the Doppler shift and multipath delay are estimated jointly by using convex programming. Simulation results show that the proposed CSR can achieve better detection probability of the number of multipaths than the eigenvalue based methods. Moreover, compared with conventional super-resolution techniques, such as MUSIC and ESPRIT methods, the proposed CSR algorithm demonstrates its advantage in root mean square error of the Doppler shift and multipath delay, especially for the closely located paths within low SNR.

Long-distance wireless local area networks (WLANs) are the key enablers of wide-area and low-cost access networks in rural areas. In a WLAN, the long propagation delay between an access point (AP) and stations (STAs) significantly degrades the throughput and creates a throughput imbalance because the delay causes unexpected frame collisions. This paper summarizes the problems caused in the medium access control (MAC) mechanism of the WLAN by a long propagation delay. We propose a MAC protocol for solving the delay-induced throughput degradation and the throughput imbalance between the uplink and the downlink in WLANs to address these problems. In the protocol, the AP extends NAV duration of CTS frame to protect an ACK frame and transmits its data frame to avoid delay induced frame collisions by piggybacking on the ACK frame transmission. We also provide a throughput model for the proposed protocol based on the Bianchi model. A numerical analysis using the proposed throughput model and simulation evaluation demonstrate that the proposed protocol increases the system throughput by 150% compared with that obtained using the conventional method, and the uplink throughput can be increased to the same level as the downlink throughput.

To improve the quality of waveforms and achieve a high input power factor (IPF) for matrix rectifier, a novel quasi sliding mode control (SMC) with adaptive compensation is proposed in this letter. Applying quasi-SMC can effective obviate the disturbances of time delay and spatial lag, and SMC based on continuous function is better than discontinuous function to eliminate the chattering. Furthermore, compared with conventional compensation, an adaptive quasi-SMC compensation without any accurate detection for internal parameters is easier to be implementated, which has shown a superior advance. Theoretical analysis and experiments are carried out to validate the correctness of the novel control scheme.

The study focuses on the adaptation problem for HTTP low-delay live streaming over mobile networks. In this context, the client's small buffer could be easily underflown due to throughput variations. To maintain seamless streaming, we present a probabilistic approach to adaptively decide the bitrate for each video segment by taking into account the instant buffer level. The experimental results show that the proposed method can significantly reduce buffer underflows while providing high video bitrates.

In this paper, we study the achievable degrees of freedom (DoF) of a multiple-input multiple-output (MIMO) multi-way relay channel with asymmetric message set that models the scenario of the two-way communication between a base station and multiple users through a relay. Under the assumption of delayed channel state information at transmitters (CSIT), we propose an amplify-and-forward relaying scheme based on the scheme proposed by Maddah-Ali and Tse to support signal space alignment, so that the available dimensions of the signal spaces at the relay and the users can be efficiently utilized. The proposed scheme outperforms the traditional one-way scheme from the perspective of DoF, and is useful to relieve the communication bottleneck caused by the asymmetric traffic load inherent in cellular networks.