This paper reviews architectures and topologies for column-parallel analog-to-digital converters (ADCs) used for CMOS image sensors (CISs) and discusses the performance of CISs using column-parallel ADCs based on figures-of-merit (FoM) with considering noise models which behave differently at low/middle and high pixel-rate regions. Various FoM considering different performance factors are defined. The defined FoM are applied to surveyed data on reported CISs using column-parallel ADCs which are categorized into 4 types; single slope, SAR, cyclic and delta-sigma ADCs. The FoM defined by (noise)2(power)/(pixel-rate) separately for low/middle and high pixel-rate regions well explains the frontline of the CIS' performance in all the pixel rates. Using the FoM defined by (noise)2(power)/(intrascene dynamic range)(pixel-rate), the effectiveness of recently-reported techniques for extended-dynamic-range CISs is clarified.

This paper presents an enhanced dual-path delta-sigma analog-to-digital converter. Compared with other architectures, the enhanced architecture increases the noise shaping order without any instability problems and displays analog complexity equivalent to the multi-stage noise shaping architecture. Our delta-sigma converter is based on this new architecture. It employs not only doubly-differential structure to reduce common-mode errors in the system-level but also delayed-feed-in structure to mitigate the timing constraint of the feedback signal. Regarding the circuit implementation, the first-order enhancement of the quantization noise shaping is achieved via the use of a switched capacitor circuit technique. The circuit is incorporated into the active adder in a low-distortion structure. The supporting clock generation circuit that provides additional phases of clocks with the enhancement block is also implemented in the CMOS logic gates. A digital dynamic element matching circuit (i.e., segmented data-weighted-average circuit) is designed to reduce mismatch errors caused by the feedback DAC of modulator. A test chip, fabricated in a 0.18-µm CMOS process, provides a signal-to-noise+distortion ratio (SNDR) of 75-dB for a 1.0-MHz signal bandwidth clocked at 40-MHz. The 2nd harmonic is -101 dB and the 3rd harmonic is -94 dB when a -4.5-dB 100-kHz input signal is applied.

Ultrasonic distance measurement using the pulse-echo method is based on the determination of the time of flight of ultrasonic waves. The pulse-compression technique, in which the cross-correlation function of a detected ultrasonic wave and a transmitted ultrasonic wave is obtained, is the conventional method used for improving the resolution of distance measurement. However, the calculation of a cross-correlation operation requires high-cost digital signal processing. This paper presents a new method of sensor signal processing within the pulse-compression technique using a delta-sigma modulated single-bit digital signal. The proposed sensor signal processing method consists of a cross-correlation operation employing single-bit signal processing and a smoothing operation involving a moving average filter. The proposed method reduces the calculation cost of the digital signal processing of the pulse-compression technique.

We developed an olfactory display to blend 8 component odors at any composition. The solenoid valves controlled by an algorithm with delta sigma modulation showed the sufficient capability. Then, we developed a system for presenting a movie together with scents. We actually made a movie with scents and evaluated it using questionnaire survey. It was found that the scene with smell attracted the experimental subjects' attention and, moreover, the contrast of the pleasant smell with the offensive one emphasized their attention. Furthermore, we established several guidelines for producing movies with scents.

This paper presents a technique for the variation of hysteresis band in delta-sigma modulation. A sinusoidal, and a random hystersis band are combined to achieve an optimal performance in terms of constant switching frequency and the harmonic spikes. The sinusoidal hysteresis band technique produces a constant switching frequency while the random hysteresis band suppresses the harmonic spikes. The effects of various variations of hysteresis band on the harmonic spectrum characteristic were described. The technique is experimented in a single-phase inverter and the harmonic peaks and the distortion of output voltage were used to measure the performance of the proposed technique.

Delta-sigma modulators (DSMs) are commonly use in high-resolution analog-to-digital converters, and band-pass delta-sigma modulators have recently been used to convert IF signals into digital signals. In particular, a quadrature band-pass delta-sigma modulator can achieve a lower total order, higher signal-to-noise ratio (SNR), and higher bandwidth when compared with conventional band-pass modulators. The current paper proposes a second-order three-bit quadrature band-pass delta-sigma modulator that can achieve a lower power consumption and better performance with a similar die size to a conventional fourth-order quadrature band-pass delta-sigma modulator (QBPDSM). The proposed system is integrated using CMOS 0.35 µm, double-poly, four-metal technology. The system operates at 13 MHz and can digitize a 200 kHz bandwidth signal centered at 4.875 MHz with an SNR of 85 dB. The power consumption is 35 mW at 3.3 V and 38 mW at 5 V, and the die size is 21.9 mm2.

The delta-sigma modulator (DSM) is an excellent choice for high-resolution analog-to-digital converters. Recently, a band-pass DSM has been a desirable choice for direct conversion of an IF signal into a digital bit stream. This paper proposes a quadrature band-pass DSM for digitizing a narrow-band IF signal. This modulator can achieve a lower total order, higher signal-to-noise ratio (SNR), and higher bandwidth when compared with conventional band-pass modulators. An experimental prototype employing the quadrature topology has been integrated in 0.6 µm, double-poly, double-metal CMOS technology with capacitors synthesized from a stacked poly structure. This system clocked at 13 MHz and digitized a 200 kHz bandwidth signal centered at 4.875 MHz with 100 dB of dynamic range. Power consumption is 190 mW at 5 V.

This paper describes a digital delay-lock Loop (DLL) to which delta-sigma (Δ Σ) modulation technique is applied in order to reduce circuit elements. The DLL is evaluated in both transient and steady-state behavior by theoretical analysis, computer simulations and circuit experiments. Not deteriorated by the internally generated Δ Σ-modulation noise, the DLL shows good tracking performance in transient response and steady-state RMS jitter of phase error against additive white Gaussian noise. Using the proposed DLL most parts of receiving circuits are realized by digital integrated circuits. After realizing the circuit, power-line communication system with spread spectrum is possibly expected in a small size with low cost.