Shigeru NAKAMURA Yoshiyasu UENO Kazuhito TAJIMA
We experimentally demonstrate the ultrafast and high-repetition capabilities of a polarization-discriminating symmetric Mach-Zehnder (PD-SMZ) all-optical switch. This switch, as well as an original symmetric Mach-Zehnder (SMZ) all-optical switch, is based on a highly efficient but slowly relaxing band-filling effect that is resonantly excited in a passive InGaAsP bulk waveguide. By using a mechanism that cancels out the effect of the slow relaxation, ultrafast switching is attained. We achieve a switching time of 200 fs and demultiplexing of 1.5 Tbps, showing the applicability of the SMZ or PD-SMZ all-optical switches to optical demultiplexing of well over 1 Tbps for the first time. High-repetition capability, which is another important issue apart from the switching speed, is also verified by using control pulses at a repetition rate of 10.5 GHz. We also discuss the use of nonlinearity in a semiconductor optical amplifier to further reduce the control-pulse energy.
This paper proposes polling-based real-time software for MPEG2 System protocol LSIs, which is a typical embedded and real-time system on a chip, and demonstrates its performance and usefulness. The polling-based real-time software is designed and optimized by analyzing application specific function requirements and deciding scheduling intervals and the execution cycles of each task. It requires neither hardware for multiple interrupt handling nor software for heavy context switching. The polling-based approach provides sufficient performance without any hardware and software overhead for a real-time application like the MPEG2 System protocol.
A new optical wavelength demultiplexer using quasi-phase-matched sum-frequency-generation (QPM-SFG) is proposed. The device consists of an optical deflector using Pockels effect and a nonlinear crystal with a periodic structure. The demultiplexing characteristics of the device composed of a LiNbO3 crystal are analyzed theoretically. Wavelength demultiplexing can be made simply by changes in the electric field applied to the deflector.
Kimio UEDA Yoshiki WADA Takanori HIROTA Shigenobu MAEDA Koichiro MASHIKO Hisanori HAMANO
This paper discusses the features of SOI/CMOS circuits in comparison with bulk/CMOS circuits. We have to design circuits with small fan outs and short wires to take advantage of high-speed and low-power SOI/CMOS devices to their fullest. We can take advantage of the SOI/CMOS structure if the ratio of the source/drain capacitances to the gate capacitances is much greater in the load capacitance. Thus, we propose a new flip-flop circuit with a smaller gate capacitance. The flip-flop circuit operates 30% faster than the previous circuit at 2.0 V. We also propose a buffer circuit having less delay disparity between the complementary output signals. The buffer circuit has the delay disparity of 18 ps at 0.2 pF and 2.0 V. We fabricated an 8-bit frequency divider and a 4-bit demultiplexer using the proposed circuits and 0.35 µm SOI/CMOS process. The 8-bit frequency divider and the 4-bit demultiplexer operate at 2.8 GHz and 1.6 GHz, respectively, at 2.0 V.
Hisato UETSUKA Kenji AKIBA Kenichi MOROSAWA Hiroaki OKANO Satoshi TAKASUGI Kimio INABA
Recently, a wavelength division multi/demultiplexing system has been viewed with keen interest because it is possible to increase the transmission capacity and system flexibility. An arrayed waveguide grating (AWG) type of Multi/demultiplexer which is one of the key components to realize such a system has been developed by using Planar Lightwave Circuits (PLCs). Newly designed optical circuits have been incorporated into the AWG to control the center wavelength and to expand the pass band width. The 3 dB pass band width is 1.4 times that of a conventional AWG. It is confirmed that the newly developed AWG has low polarization dependence, low temperature dependence and high reliability.
Masaaki SHIMADA Norio HIGASHISAKA Akira OHTA Kenji HOSOGI Kazuo KUBO Noriyuki TANINO Tadashi TAKAGI Fuminobu HIDANI Osamu ISHIHARA
GaAs 10 Gb/s 64:1 Multiplexer/Demultiplexer chip sets have been successfully developed. The 64-bit 156 Mb/s parallel data output or input of these chip sets can be directly connected to CMOS LSIs. These chip sets consist of a 10Gb/s 4: 1 MUX IC, a 10 Gb/s 1: 4 DEMUX IC, four 2.5 Gb/s 16: 1 MUX LSIs and four 2.5 Gb/s 1: 16 DEMUX LSIs. This multi-chip construction is adopted for low power dissipation and high yield. The basic circuit employed in the 10 Gb/s4: 1 MUX/DEMUX ICs is an SCFL circuit using 0.4 µm-gate FETs with a power supply of -5.2 V, and that in 2.5 Gb/s 16: 1 MUX/DEMUX LSIs is a DCFL circuit using 0.6 µm-gate FETs with a power supply of -2.0 V. These chip sets have functions for synchronization among these ICs and to enable bit shift to make the system design easier. In the 10 Gb/s 4: 1 MUX IC, a timing adjuster is adopted. This timing adjuster can delay the timing of the most critical path by 50 ps. Even if the delay times are out of order due to fluctuations in process, temperature, power supply voltage and other factors, this timing can be revised and the 4: 1 MUX IC can operate at 10 Gb/s. Furthermore, a 48-pin quad flat package for 10 Gb/s 4: 1 MUX/DEMUX ICs has been newly developed. The measured insertion loss is 1.7 dB (at 10 GHz), and the isolation is less than -20 dB (at 10 GHz). These values are sufficient in practical usage. Measurements of these chip sets show desirable performance at the target 10 Gb/s. The power dissipations of the 64: 1 MUX/DEMUX chip sets are 10.3 W and 8.2 W, respectively. These chip sets is expected to contribute to high speed telecommunication systems.
Kimio UEDA Nagisa SASAKI Hisayasu SATO Shunji KUBO Koichiro MASHIKO
This paper describes an 8:1 multiplexer and a 1:8 demultiplexer for fiber optic transmission systems. These chips incorporate new architectures having a smaller hardware and enabling the use of a lower supply voltage. The multiplexer and the demultiplexer are fabricated using 0.8 µm silicon-bipolar process with a double polysilicon self-aligned structure. The multiplexer operates at a bit rate of up to 3.0 Gb/s, while the demultiplexer operates at a bit rate of up to 4.1 Gb/s. The multiplexer consumes 272 mW and the demultiplexer consumes 388 mW under the power supplies of VEE=-4.0 V and VTT=-2.0 V. These values are the smallest so far above 2.5 Gb/s which is the standard of the Level-16 of the synchronous transfer mode (STM-16).
Masatoshi SUZUKI Noboru EDAGAWA Hidenori TAGA Hideaki TANAKA Shu YAMAMOTO Yukitoshi TAKAHASHI Shigeyuki AKIBA
Feasibility of 20 Gbit/s single channel transoceanic soliton transmission systems with a simple EDFA repeaters configuration has been studied. Both a simple and versatile soliton pulse generator and a polarization insensitive optical demultiplexer, which can provide a almost square shape optical gate with duration of full bit time period, have been proposed and demonstrated by using sinusoidally modulated electroabsorption modulators. The optical time-division multiplexing/demultiplexing scheme using the optical demultiplexer results in drastic improvement of bit error rate characteristics. We have experimentally confirmed that the use of alternating-amplitude solitons is an efficient way to mitigate not only soliton-soliton interaction but also Gordon-Haus timing jitter constraints in multi-ten Gbit/s soliton transmission. Timing jitter reduction using relatively wide band optical filter bas been investigated in 20 Gbit/s loop experiments and single-carrier, single-polarization 20 Gbit/s soliton data transmission over 11500 km with bit error rate of below 10-9 has been experimentally demonstrated, using the modulator-based soliton source, the optical demultiplexer, the alternation-amplitude solitons, and wide-band optical filters. Obtained 230 Tbit/skm transmission capacity shows the feasibility of 20 Gbit/s single channel soliton transoceanic systems using fully practical technologies.
Kiyoshi KISHIOKA Yoshinori YAMAMOTO
In this paper, a novel coupler-type wavelength demultiplexer composed of the K+-ion diffused waveguides, which has an adjustment function for optimizing the diffusion depth, is proposed to achieve reliably the high extinction ratio. The optimization in the diffusion depth is made by repeating the K+-ion diffusion and extinction-ratio measurement alternatively, and the high extinction ratios more than 20 dB are measured reliably at both operation wavelengths of 0.6328 and 0.83 µm. Experimental results on the polarization dependence in the extinction-ratio adjustment are also reported.
Kiyoshi KISHIOKA Heihachiro OCHIAI
In this paper, a novel Y-junction type demultiplexer utilizing a stratified-waveguide configuration in the branching region is proposed for the purpose of improving the extinction ratio. A high extinction ratio of about 20 dB is achieved at 0.6328 µm and 0.83 µm operation wavelengths both for the TE and TM modes. The properties of the new type branchig waveguides which consist of the diffused waveguide and the striploaded waveguide are described to explain the operation principle. Simulation results by the BPM are also shown to check the designed values of the waveguide parameters.