Dry etching is one of the elemental technologies for the fabrication of optical devices. In order to obtain the desired shape using the dry etching process, it is necessary to understand the reactivity of the materials being used to plasma. In particular, III-V compound semiconductors have a multi-layered structure comprising a plurality of elements and thus it is important to first have a full understanding of the basic trends of plasma dry etching, the plasma type and the characteristics of etching plasma sources. In this paper, III-V compound semiconductor etching for use in light sources such as LDs and LEDs, will be described. Glass, LN and LT used in the formation of waveguides and MLA will be introduced as well. And finally, the future prospects of dry etching will be described briefly.

The individual steps of UV imprint lithography have been explained in detail from the points of manufacturing nano-structures. The applications to photonic devices have been also introduced.

The dry etching resistance of ArF resist patterns was improved by irradiating vacuum ultraviolet (VUV) light with a wavelength of 172 nm to ArF resist patterns in N2 atmosphere. The density of C=O bonds of the resists is decreased, and the dry etching rate of resist is also decreased after VUV irradiation. The line width shrinkage by the electron beam irradiation of CD-SEM was greatly improved from 9 nm to 2 nm, and LER (Line Edge Roughness) of resist patterns was approximately 2 nm improved from 8.4 nm to 6.5 nm under VUV irradiation. Using VUV cure, the dry etching pattern of a SiN film showed a rectangle-like cross-sectional view, and indicated almost the same LER value as the resist mask pattern. The VUV cure technique is an attractive method of fine resist pattern fabrication by ArF lithography.

A novel method has been developed to improve the dry etching selectivity of aluminum alloy with respect to photoresist by implanting ions into the patterned photoresist. The selectivity becomes 7.5, which is 5 times higher than that of the unimplanted case. Accordingly, this technology is very promising for fabricating multi-level interconnections in sub-half micron LSIs.

The realization of scientific manufacturing of ULSIs in the 21st century will require the development of a technical infrastructure of "Ultra Clean Technology" and the firm establishment of the three principles of high performance processes. Three principles are 1)Ultra Clean Si Wafer Surface, 2)Ultra Clean Processing Environment, and 3)Perfect Parameter controlled process. This paper describes the methods of resolving the problems inherent in Ultra Clean Technology, taking as examples issues in quarter-micron or more advanced semiconductor process and manufacturing equipment, particularly when faced with the challenges of plasma dry etching. Issues indispensable to the development of tomorrow's highly accurate and reliable plasma dry etching equipment are the development of technologies for the accurate measurement of plasma parameters, ultra clean gas delivery systems, chamber cleaning technology on an in-situ basis, and simulating the plasma chemistry.This paper also discusses the standardization of semiconductor manufacturing equipment, which is considered one of the ways to reduce the steep rise in production line construction costs. The establishment of Ultra Clean Technology also plays a vital role in this regard.

A Pt-based gate and photochemical dry etching were developed to fabricate N-InAlAs/InGaAs HEMT ICs. The N-InAlAs/Pt contact showed a Schottky barrier at 0.82 eV, about 0.3 eV larger than ΔEc, and nearly ideal I-V characteristics. Its main disadvantage was the excess penetration of Pt into InAlAs. We proposed a thin-Pt/Ti/Au multilayer gate, more thermally stable than the thick-Pt gate, where Ti layer suppresses the above problem with Pt. The multilayer gate also showed a Schottky barrier (φ) of 0.83 eV and an edeality dactor of 1.1. The high φ value makes it possible to fabricate an E-mode N-InAlAs/InGaAs HEMT. We also developed photochemical selective dry etching using CH3Br gas and a low-pressure mercury lamp. The etching selectivity was 25 at an etch rate of 17 nm/min for InGaAs and 0.7 nm/min for InAlAs. The 1.2-µm-gate E-mode HEMT fabricated using the Pt-based gate and photochemical etching had an excellent peak transconductance of 620 mS/mm with a threshold voltage of +0.03 V. The standard deviation of the threshold voltage of E-mode HEMTs on a 2-inch wafer was 20 mV at an average of +0.088 V. These results indicate the effectiveness of the Pt-based gate and photochemical etching for fabricating N-InAlAs/InGaAs HEMT ICs.