We report on the fabrication of coplanar dual-gate ZnO thin-film transistors with 200-nm thickness SiNx for both top and bottom dielectrics. The ZnO film was deposited by RF magnetron sputtering on SiO2/Si substrates at 100. And the thickness of ZnO film is compared with 100-nm and 40-nm. This TFT has a channel width of 100-µm and channel length of 5-µm. The fabricated coplanar dual-gate ZnO TFTs of 40-nm-thickness exhibits a field effect mobility of about 0.29 cm2/V s, a subthreshold swing 420 mV/decade, an on-off ratio 2.7107, and a threshold voltage 0.9 V, which are greatly improved characteristics, compared with conventional bottom-gate ZnO TFTs.

A Q-band high gain and low noise Variable Gain Amplifier (VGA) module using dual gate AlGaAs/InGaAs pseudomorphic HEMTs has been developed. The dual gate HEMT can be fabricated by the same process of the single gate HEMT which has the gate length of 0.15 µm. The Q-band VGA module consists of a 1-stage low noise amplifier (LNA) MMIC using a single gate HEMT and a 2-stage VGA MMIC using dual gate HEMTs. During the design, an accurate noise modeling is introduced to achieve low noise performance. A fully passivated film is employed to achieve reliability. The VGA module has a gain of more than 20 dB from 41 GHz to 52 GHz and a maximum gain of 24.5 dB at 50 GHz. A gain control range of more than 30 dB is achieved in the same frequency range. A phase deviation is less than 10 degrees in 10 dB gain control range. A minimum noise figure of 1.8 dB with an associated gain of 22 dB is achieved at 43 GHz and the noise figure is less than 2.5 dB with associated gain of more than 20 dB from 41 GHz to 46 GHz when biased for low noise figure. This performance is comparable with the best data ever reported for LNAs at Q-band including both GaAs based HEMTs and InP based HEMTs.

A full CMOS cell technology for high density SRAMs has been developed. A 0.4 µm n+/p+ spacing has been achieved by a shallow trench isolation with a retrograde and a shallow well design. Dual gate 0.35 µm n- and p-channel MOSFETs were used for the high density full CMOS SRAM cell. The side-wall inversion problem to which MOSFETs are subject due to the trench isolation structure has been controlled by combining taper angled trench etching and a rounded trench edge shape. A dual gate 0.4 µm nMOS/pMOS spacing has also been accomplished with no lateral gate dopant diffusion by an enlarged grain size tungsten polycide gate structure. These techniques can resolve the bottleneck problem of full CMOS SRAM cell size reduction, and realize a competitive cell size against conventional polysilicon resistor load SRAM cell (E/R type cell) or thin-film-transistor load SRAM cell (TFT type cell) structures. A test chip of a 256 k bit full CMOS SRAM was fabricated to verify the process integration of the shallow trench isolation with the retrograde shallow well design and the dual gate CMOS structure. It has been recognized that the above techniques are possible solutions for deep sub-micron high density full CMOS SRAM cell structure.