This paper proposes a secure electronic sealed-bid auction protocol (SEAP) that provides an auction service on the Internet by combining three providers: an auction service provider, a key service provider, and a time service provider. The SEAP uses public key cryptography and the concept of a time-key certificate. The most important property of this protocol is that time-dependent security requirements can be strictly satisfied. The SEAP satisfies the following nine security requirements: (a) no one can deny having made a bid; (b) the protocol should be secure against malicious acts; (c) no bidder can act for another bidder; (d) no one can know who else is bidding until the time comes for the bids to be opened; (e) no one can discover the contents of any of the bids until the time comes for the bids to be opened; (f) the successful bid must have been submitted before the bidding deadline; (g) all bidders can verify that the auction policy has been correctly implemented; (h) the successful bidder can be identified without being required to make himself or herself known; and (i) the bidding contents cannot be altered. The protocol consists of three subprotocols: the Registration Subprotocol, the Bidding Subprotocol, and the Auction Subprotocol. The protocol parameters and algorithm are described in detail.

The advantages of DRAM-logic integration were demonstrated through a comparison with a conventional separate-chip architecture. Although the available DRAM capacity is restricted by chip size, the integration provides a high throughput and low I/O-power dissipation due to a large number of on-chip I/O lines with small load capacitance. These features result in smaller chip counts as well as lower power dissipation for systems requiring high data throughput and having relatively small memory capacity. The chip count and I/O-power dissipation were formulated for multimedia systems. For the 3-D computer graphics system with a frame of 12801024 pixels requiring a 60-Mbit memory capacity and a 4.8-Gbyte/s throughput, DRAM-logic integration enabled a 1/12 smaller chip count and 1/10 smaller I/O-power dissipation. For the 200-MIPS hand-held portable computing system that had a 16-Mbit memory capacity and required a 416-Mbyte/s throughput, DRAM-logic integration enabled a 1/4 smaller chip count and 1/17 smaller I/O-power dissipation. In addition, innovative architectures that enhance the advantages of DRAM-logic integration were discussed. Pipeline access for a DRAM macro having a cascaded multi-bank structure, an on-chip cache DRAM, and parallel processing with a reduced supply voltage were introduced.

This paper presents a technique to determine prime implicants in multi-level combinational networks. The method is based on a graph representation of Boolean functions called AND/OR reasoning graphs. This representation follows from a search strategy to solve the satisfiability problem that is radically different from conventional search for this purpose (such as exhaustive simulation, backtracking, BDDs). The paper shows how to build AND/OR reasoning graphs for arbitrary combinational circuits and proves basic theoretical properties of the graphs. It will be demonstrated that AND/OR reasoning graphs allow us to naturally extend basic notions of two-level switching circuit theory to multi-level circuits. In particular, the notions of prime implicants and permissible prime implicants are defined for multi-level circuits and it is proved that AND/OR reasoning graphs represent all these implicants. Experimental results are shown for PLA factorization.

Irreducible components of canonical graphs for second order spectral null constraints at a rational submultiple of the symbol frequency fsk/n are studied where fs is the symbol frequency. We show that if n is prime then a canonical graph consists of disjoint irreducible components. We also show that the number of irreducible components of a canonical graphs is finite if n is prime. For the case n = 2 and p O mod n, all aperiodic irreducible components are identified explicitly where p is a parameter of a canonical graph.

Producing realistic images and animations of flames is one of the most interesting subjects in the field of computer graphics. In a recent paper, we described a two-dimensional particle-based visual method of simulating flames. In the present paper, we first extend the simulation method, without losing any of its desirable features, in such a way that it functions in three-dimensional space. We then present an efficient method of producing an image of the scene, including flames acting as volume light sources, which normally requires a large amount of computing time in the usual simulation approaches. Finally, we demonstrate the capabilities of our visual simulation method by showing sample images generated by it, which are excerpted from an animation.

This paper deals with two different quantitative inversion algorithms for reconstructing the complex permittivity profile of bounded inhomogeneous objects from measured scattered field data. The first algorithm involves an imaging method with single frequency excitation and multiincidence illumination and the second algorithm involves a method with synthetic pulse (multifrequency mode) excitation for objects surrounded by freespace or buried in stratified half-space media. Transmission or reflection imaging protocols are considered depending on aimed applications: microwave imaging in free-space from far-field data for target identification, microwave imaging from near-field data for nondestructive testing (NDT), microwave tomography of buried objects for mine detection and localization, civil engineering and geophysical applications. And Edge-Preserving regularization scheme leading to a significant enhancement in the image reconstructions is also proposed. The methods are illustrated with synthetic and experimental data.

A family of nonce-based authentication and key distribution protocols based on the trusted third-party model are proposed which are not only efficient on the view points of computation and communication, but also secure against on-line and off-line password guessing attacks. A new concept of implicit or indirect challenge-response authentication which can be used to combine the processes of identify authentication and data integrity assurance during key distribution and to make the entire protocol be more concise and efficient is introduced in this paper. In the proposed family of protocols, specific protocol can be chosen such that the secure session key to be distributed is selected by specific participant in the protocol. Detailed security analyses of every protocols are given.

Entropy coding/decoding are implemented on FPGAs as a fast and flexible system in which high-level synthesis technologies are key issues. In this paper, we propose scheduling and allocation algorithms for behavioral descriptions of entropy CODEC. The scheduling algorithm employs a control-flow graph as input and finds a solution with minimal hardware cost and execution time by merging nodes in the control-flow graph. The allocation algorithm assigns operations to operators with various bit lengths. As a result, register-transfer level descriptions are efficiently obtained from behavioral descriptions of entropy CODEC with complicated control flow and variable bit lengths. Experimental results demonstrate that our algorithms synthesize the same circuits as manually designed within one second.

A modified cryptographic key assignment scheme for the dynamic access control in a group-oriented user hierarchy is presented. In the partially ordered set (poset, for short) user hierarchy (GjGi) embedded in a group-oriented (t, n) threshold cryptosystem, the source group Gi has higher security clearance to access the information items held in the target group Gj. If a target group Gj has multipe paths reachable from a source group Gi, we must choose the least cost path to rapidly resolve the dynamic access control problem Furthermore, multiple threshold values are also considered in order to meet the different security requirements.

This paper describes technological and operational issues of an image-art-on-demand system, which provides visitors with high-definition images of fine art in a virtual gallery. The system is presented as a typical example of multimedia information service systems on IP over ATM network. The high-definition images of fine arts from a database are interactively selected in a virtual gallery which is generated by an advanced computer graphics (CG) workstation. The generated images of the virtual gallery are transmitted by MPEG-2 over TCP/IP on ATM at 30 frames per second. This system was opened from January 1996 to March 1997 as one project of NTT's joint utilization tests of multimedia communications. As far as we know, this system is the first real-time image-art-on-demand system using MPEG-2 on IP over ATM-WAN to be exhibited to the general public.

A novel cryptographic key assignment scheme for dynamic access control in a user hierarchy is presented. Based on Rabin's public key system and Chinese remainder theorem, each security class SCi is assigned a secret key Ki and some public parameters. In our scheme, a secret key is generated in a bottom-up manner so as to reduce the computation time for key generation and the storage size for public parameters. We also show that our proposed scheme is not only secure but also efficient.

The graph partitioning problem is a famous combinatorial problem and has many applications including VLSI circuit design, task allocation in distributed computer systems and so on. In this paper, a novel neural network for the m-way graph partitioning problem is proposed where the maximum neuron model is used. The undirected graph with weighted nodes and weighted edges is partitioned into several subsets. The objective of partitioning is to minimize the sum of weights on cut edges with keeping the size of each subset balanced. The proposed algorithm was compared with the genetic algorithm. The experimental result shows that the proposed neural network is better or comparable with the other existing methods for solving the m-way graph partitioning problem in terms of the computation time and the solution quality.

The computers are connected with each other by the network as a result of the progress of technology in the field of the computer and network, and then all of the data to be processed are transferred quickly and at the real-time through the computer network. However the user can use the computer system at any time, the user must go to the location of the computer system to use the computer resources. The necessities for using the computer system occur anywhere and anytime in spite of the location of the computer system. For this requirement the mobile computing environment (MCE) is expected strongly. In this paper we introduce the model of MCE and discuss the need of the user authentication at entering and logging-in the network in MCE only with a user ID. We propose the method of a user ID assignment from which a server ID can be decided by a simple logical operation. Also, we propose a protocol for a user authentication in MCE and discuss the robustness of security against the various attacking on the route.

The technique of common-multiplicand multiplication, CMM, is modified and the similar approach is utilized to enhance the performance of a recently proposed fast exponentiation algorithm by exponent decomposition. On average, the improved exponentiation, its original version, and the traditional right to left binary exponentiation algorithm take 1.292m+11,1.375m+3, and 1.5m multiplications, respectively where m is the bit length of the exponent. Finally, it is shown how to improve the overall performance of an exponentiation by employing the improved exponentiation algorithm, the improved CMM algorithm , and any general purpose fast multiplication algorithm.

We consider the problem of designing a physically diverse network that can support any two simultaneous node-to-node traffic flow requirements as called for by special events such as communication link failures or surges in network traffic. The design objective is to obtain a network with the minimum level of network capacity, yet robust enough to handle any two simultaneous traffic flow requirements between any nodes. To arrive at the minimum necessary network capacity,we introduce the concept of nodal requirement. Based on nodal requirements, we can build what may be called uniform protection subnetworks for equal nodal requirements. Successive uniform protection subnetworks can be built for incremental nodal requirements. This direct approach supersedes the extant work on building fully connected networks or loops from maximum spanning trees that can cope with only one traffic flow requirement. Our nodal requirements approach generalizes well to multiple simultaneous traffic flow requirements. Hub subnetworks are introduced to provide protection for networks with a unique node that has the largest nodal requirement. Further, a heuristic is considered and analyzed that assigns edge capacities of the protection network directly based on the largest two traffic flow requirements incident on the end nodes of an edge. The heuristic is attractive in being simple to implement.

In this paper a cyclic place-timed controlled marked graph (PTCMG), which is an extended class of a cyclic controlled marked graph (CMG), is presented as a model of discrete event systems (DESs). In a PTCMG, time constraints are attached to places instead of transitions. The time required for a marked place to be marked again is represented in terms of time constraints attached to places. The times required for an unmarked place to be marked under various controls, are calculated. The necessary and sufficient condition for a current marking to be in the admissible marking set with respect to the given forbidden condition is provided, as is the necessary and sufficient condition for a current marking to be out of the admissible marking set with respect to the forbidden condition in one transition. A maximally permissive state feedback control is synthesized in a PTCMG to guarantee a larger admissible marking set than a CMG for most forbidden state problems. Practical applications are illustrated for a railroad crossing problem and an automated guided vehicle (AGV) coordination problem in a flexible manufacturing facility.

In this paper, we consider the following node-to-set disjoint paths problem: given a node s and a set T = {t1,...,tk} of k nodes in a k-connected graph G, find k node-disjoint paths s ti, 1 i k. We give an O(n2) time algorithm for the node-to-set disjoint paths problem in n-dimensional star graphs Gn which are (n - 1)-connected. The algorithm finds the n - 1 node-disjoint paths of length at most d(Gn) + 1 for n 4,6 and at most d(Gn) + 2 for n = 4,6, where d(Gn) = 3(n-1)/2 is the diameter of Gn. d(Gn) + 1 and d(Gn) + 2 are also the lower bounds on the length of the paths for the above problem in Gn for n 4,6 and n = 4,6, respectively.

This paper proposes a unified approach by means of the binary decision diagram, BDD in short, to solve #P-hand problems of counting the number of paths between two terminals in undirected and directed graphs. Our approach provides algorithms running in O (2O (n) ) time for typical planar graphs such as grid graphs. In fact, for any class of graphs having a good elimination ordering, this paradigm provides efficient solutions.

This paper describes a new approach to the scheduling problem that assigns tasks of a parallel program described as a task graph onto parallel machines. The approach handles interprocessor communication and heterogeneity, based on using both the theoretical results developed so far and a lookahead scheduling strategy. The experimental results on randomly generated task graphs demonstrate the effectiveness of this scheduling heuristic.

Topological sorting is, given with a directed acyclic graph G = (V, E), to find a total ordering of the vertices such that if (u, v) E then u is ordered before v. Instead of finding total orderings, we wish to find out how many total orderings exist in a given directed acyclic graph G = (V, E). Here we call a total ordering as legal sequence and the problem as legal sequence number problem. In this paper, we first propose theorems on equivalent transformation of graphs with respect to legal sequence number. Then we give a formula to calculate legal sequence number of basic series-parallel digraphs and a way of the calculation for general series-parallel digraphs. Finally we apply our results to show how to obtain legal sequence number for a class of extended series-parallel digraphs.