This paper proposes a single coil active shielding method of wireless unmanned aerial vehicle charger for leakage magnetic field reduction. A proposed shielding system eliminates the leakage magnetic field generated from the transmitting and receiving coils by generating the cancelling magnetic field. In order to enhance shielding effectiveness and preserve power transfer efficiency, shielding coil design parameters including radius and turns will analyze. Based on the analysis of coil design, shielding effectiveness and power transfer efficiency will estimate. In addition, shielding current control method corresponding to leakage magnetic field strength and phase will describe. A proposed shielding system has verified by simulations and experiments in terms of the total shielding effectiveness and power transfer efficiency measurements. The simulation and experimental results show that a proposed active shielding system has achieved 68.85% of average leakage magnetic field reduction with 1.92% of power transfer efficiency degradation. The shielding effectiveness and power transfer efficiency variation by coil design has been experimentally verified.

Optimal loads and maximum achievable efficiency for multiple-receiver inductive power transfer (IPT) system have been formulated by theoretical studies in literatures. This paper presents extended analysis on system behavior at optimal load condition and extensive S-parameter evaluation to validate the formulas. Our results confirm that at the optimal load condition, the system is in a resonance state; the impact of cross-coupling among receivers is completely mitigated; and the efficiency reaches its maximum expressed by an efficiency angle tangent, in an manner analogous to the well-known kQ-theory for single-receiver IPT. Our contributions do not lie in practical applications of multiple-receiver IPT but in establishing principles for design and benchmarking the system.

This paper investigates receive power control for multiuser inductive power transfer (IPT) systems with a single-frequency coil array. The primary task is to optimize the transmit coil currents to minimize the total input power, subject to the minimum receive powers required by individual users. Due to the complicated coupling mechanism among all transmit coils and user pickups, the optimization problem is a non-convex quadratically constrained quadratic program (QCQP), which is analytically intractable. This paper solves the problem by applying the semidefinite relaxation (SDR) technique and evaluates the performance by full-wave electromagnetic simulations. Our results show that a single-frequency coil array is capable of power control for various multiuser scenarios, assuming that the number of transmit coils is greater than or equal to the number of users and the transmission conditions for individual users are uncorrelated.

Wafer-level testing is a well established solution for detecting manufacturing errors and removing non-functional devices early in the fabrication process. Recently this technique has been facing a number of challenges, resulting from increased complexity of devices under test, larger number and higher density of pads or bumps, application of mechanically fragile materials, such as low-k dielectrics, and ever developing packaging technologies. Most of these difficulties originate from the use of mechanical probes, as they limit testing speed, impose performance limitations and add reliability issues. Earlier work focused on relaxing these constraints by removing mechanical probes for data transmission and DC signal measurement and replacing them with non-contact interfaces. In this paper we extend this concept by adding a capability of transferring power wirelessly, enabling non-contact wafer-level testing. In addition to further improvements in the performance and reliability, this solution enables new testing scenarios such as probing wafers from their backside. The proposed system achieves 6 W/25 mm2 power transfer density over a distance of up to 0.32 mm, making it suitable for non-contact wafer-level testing of medium performance CMOS integrated circuits.