This study discusses the feasibility to estimate the concentration level of Japanese document workers using computer. Based on the previous findings that dual-task scenarios increase reaction time, we hypothesized that the Kana-Kanji conversion confirmation time (KKCCT) would increase due to the decrease in cognitive resources allocated to the document task, i.e. the level of concentration on the task at hand. To examine this hypothesis, we conducted a set of experiments in which sixteen participants copied Kana text by typing and concurrently converted it into Kanji under three conditions: Normal, Dual-task, and Mental-fatigue. The results suggested the feasibility that KKCCT increased when participants were less concentrated on the task due to subtask or mental fatigue. These findings imply the potential utility of using confirmation time as a measure of concentration level in Japanese document workers.

This paper describes key design technology issues as general ideas, rather than for specific fields, with a view to realizing better technology for the future. This paper also discusses the scope of the vision we should adopt, the factors we should be conscious of, and how we should design future systems. The key ideas arise from the belief that technology should be designed in the context of the environment with intellect behind it.

IP (Intellectual Property) reuse plays an important role in modern IC design so that IP Protection (IPP) technique is get concerned. In this paper, we introduce a new efficient watermarking system for IPP on post-layout design stage. The signature (which indicates the designer) is encrypted with a secret key by DES (Data Encryption Standard) to produce a bit string, which is then embedded into the layout design as constraints by using a specific incremental router. Once the design is watermarked successfully, the signature can be extracted accurately by the system. The system also has a strong resistance to the attack on watermarking due to the DES functionality. This watermarking technique uniquely identifies the circuit origin, yet is difficult to be detected or fabricated without our tool. We evaluated the watermarking system on IBM-PLACE 2.0 benchmark suites. The results show the system robustness and strength: the system success probability achieves 100% in suitable time with no extra area and wire length cost on design performances.

This paper proposes a novel boundary scan test scheme for intellectual property (IP) core identification via watermarking. The core concept is embedding a watermark identification circuit (WIC) and a test circuit into the IP core at the behavior design level. The procedure depends on current IP-based design flow. This scheme can detect the identification of the IP provider without the need to examine the microphotograph after the chip has been manufactured and packaged. This scheme can successfully survive synthesis, placement, and routing and identify the IP core at various design levels. Experimental results have demonstrated that the proposed approach has the potential to solve the IP identification problem.

Several IP cells are available in the market to implement 8051-compliant microcontroller in embedded systems. Yet they frequently lack features that have become a key point in such systems, like power optimization. This paper aims at lowering the power consumption of an 8051 IP core while keeping unaltered performances, through Register Transfer Level techniques such as clustered clock gating, operand isolation and state encoding. This approach preserves the IP high-reusability and technology independence, as it only consists of modifications to the source VHDL code. A total power reduction of about 40% is achieved, with limited area overhead.

Although watermarking techniques have been extensively developed for natural videos, little progress is made in the area of graphics animation. Following the former successful MPEG-1 and MPEG-2 coding standards that provide efficient representations of natural videos, the emerging MPEG-4 standard incorporates new coding tools for 2D mesh animation. Graphics animation information is crucial for many applications and may need proper protection. In this paper, we develop a watermarking technique suitable for MPEG-4 2D mesh animation. The proposed method is based on the multiresolution analysis of 2D dynamic mesh. We perform wavelet transform on the temporal sequence of the node points to extract the significant spectral components of mesh movement, which we term the "feature motions. " A binary watermark invisibly resides in the feature motions based on the spread-spectrum principle. Before watermark detection, a spatial-domain least-squares registration technique is used to restore the possibly geometrically distorted mesh data. Each watermark bit is then detected by hard decision with cryptographically secure keys. We have tested the proposed method with a variety of attacks, including affine transformations, temporal smoothing, spectral enhancement and attenuation, additive random noise, and a combination of the above. Experimental results show that the proposed watermarks can withstand the aforementioned attacks.

In SoC (system-on-a-chip) design, interfacing among IP (Intellectual Property) blocks is one of the most important issues. Since most IP's are provided by different vendors, they generally have different interface schemes and different operating frequencies. In this paper, we propose a new interface synthesis method with two features: 1) generation of the interface between IP's with different operating frequencies, and 2) minimization of the hardware resource required for the interface. We have demonstrated the proposed algorithm through its application to an MP3 decoder design example, where the IIS (Inter-IC Sound)-to-PCI (Peripheral Component Interconnect) protocol converter was successfully implemented using the proposed method.

We present a new technique for hierarchical intellectual property (IP) protection using partially-mergeable cores. The proposed core partitioning technique guarantees 100% protection of critical-IP, while simplifying test generation for the logic that is merged with the system. Since critical-IP is tested using BIST, the controllability and observability of internal lines in the core are enhanced, and test application time is reduced. Case studies using the ISIT-DLX and Picojava processor cores demonstrate the applicability of our technique.

Today's enterprise information systems are modeled on the client/server paradigm over LANs interconnected by WANs, but it involves problems of network management costs and complicated management jobs. So efficient network management is strongly required for LANs interconnected by WANs. In this paper, we describe a hierarchical enterprise network management system for LANs interconnected by WANs, based upon analysis of LAN management operations. This network management system has a hierarchical model with three levels, i.e., center level, area level, and user-site level. We also describe how this system was implemented as a nation-wide corporate network with many LAN sites, emphasizing on its functional structure. This network's success has confirmed usefulness of the management system.