A floorplan specifies the layout of modules in very large scale integration (VLSI) design, and a new code, called the EQ-sequence, for representing a floorplan is presented in this paper. The EQ-sequence is based on a Q-sequence. The EQ-sequence can preserve the adjacent relationships of rooms on a floorplan, but the Q-sequence cannot. The algorithms for encoding, moving and decoding of an EQ-sequence are introduced. With the EQ-sequence, we can check whether two modules abut each other on a floorplan. It has been proved that any floorplan of n rooms is uniquely encoded by an EQ-sequence and any EQ-sequence is uniquely decoded to a floorplan, both in O(n) time.

A large memory is typically designed with multiple identical memory blocks for reducing delay and power. The circuit verification of individual memory blocks can be effectively handled by the Symbolic Trajectory Evaluation (STE) approach. However, if multiple memory blocks are integrated into a single system, the STE approach cannot verify it economically. This paper introduces algorithms for verifying block-level connectivity of memories. The verification time of a large memory can be reduced drastically by using bottom-up verification scheme. That is, a memory block is first verified thoroughly, and then only the interconnection between memory blocks of the large memory needs to be verified. The proposed verification algorithms require (3n+2(log2n+1)+3log2m) Read/Write operations for a 2nm-bit memory, where n and m are the address width and data width, respectively. Also, the algorithms can verify 100% of the inter-port and intra-port signal misplaced faults of the address, data input, and data output ports.

As audio and video applications have proliferated on the Internet, transcoding proxy caching has been considered as an important technique for improving network performance, especially for mobile networks. Due to several new emerging factors in the transcoding proxy, existing methods for proxy placement for web caching cannot be simply applied to solve the problem of proxy placement for transcoding proxy caching. This paper addresses the problem of proxy placement for coordinated en-route transcoding proxy caching for tree networks. We propose a model for this problem by including the new emerging factors in the transcoding proxy and present optimal solutions for this problem with/without constraints on the number of transcoding proxies using dynamic programming. Finally, we implement our algorithm and evaluate our model on various performance metrics through extensive simulation experiments. The implementation results show that our model outperforms the existing model for transcoding proxy placement for linear topology, as well as the random proxy placement model. The average improvements of our model over the other models are about 7.2 percent and 21.4 percent in terms of all the performance metrics considered.

Sensor nodes are prone to failure and have limited power capacity, so the evaluation of fault tolerance and the creation of technology for improved tolerance are among the most important issues for wireless sensor networks. The placement of sensor nodes is also important, since this affects the availability of nodes within sensing range of a target in a given location and of routes to the base station. However, there has been little research on the placement of sensor nodes. Furthermore, all research to date has been based on deterministic node placement, which is not suitable when a great many sensor nodes are to be placed over a large area. In such a situation, we require stochastic node placement, where the sensor-positions are in accord with a probability density function. In this paper, we examine how fault tolerance can be improved by stochastic node placement that produces scale-free characteristics, that is, where the degree of the nodes follows a power law.

In CC-NUMA multiprocessor systems, it is important to reduce the remote memory access time. Based upon the fact that increasing the size of the LRU second-level (L2) cache more than a certain value does not reduce the cache miss rate significantly, in this paper, we propose two split L2 caches to utilize the surplus of the L2 cache. The split L2 caches are composed of a traditional LRU cache and another cache to reduce the remote memory access time. Both work together to reduce total L2 cache miss time by keeping remote (or long-distance) blocks as well as recently used blocks. For another cache, we propose two alternatives: an L2-RVC (Level 2 - Remote Victim Cache) and an L2-DAVC (Level 2 - Distance-Aware Victim Cache). The proposed split L2 caches reduce total execution time by up to 27%. It is also found that the proposed split L2 caches outperform the traditional single LRU cache of double size.

In recent years, not only functionality but also usability have come to be required in software. In order to develop a highly usable GUI (Graphical User Interface) application, it is effective that end users evaluate their GUI and the results of the evaluation are reflected on the original GUI. In these cases, it is necessary to replace a widget with another widget, and to reconnect the new GUI part with the original body part. When widgets are replaced, the operations are usually changed, but the roles of the GUI are seldom changed. In this research, we propose a development method for GUI applications with easy operations and also a method of automatic reconnection between GUI parts and new body parts. This reconnection is realized by classifying widgets according to their roles and by replacing methods of widgets with abstract methods categorized by common roles.

Solution space smoothing allows a local search heuristic to escape from a poor, local minimum. In this paper, we propose a technique that can smooth the rugged terrain surface of the solution space of a placement problem. We test the smoothing heuristics for MCNC benchmarks, and for VLSI placement with pre-placed modules and placement with consideration of congestion. Experiment results demonstrated that solution space smoothing is very efficient for VLSI module placement, and it can be applied to all floorplanning representations proposed so far.

The traditional way of approaching device-level placement problems for analog layout is to explore a huge search space of absolute placement representations, where cells are allowed to illegally overlap during their moves. This paper presents a novel exploration technique for analog placement, operating on a subset of tree representations of the layout, where the typical presence of an arbitrary number of symmetry groups of devices is directly taken into account during the search of the solution space. The efficiency of the novel approach is due to the use of red-black interval trees, data structures employed to support operations on dynamic sets of intervals.

This paper presents a novel data placement and retrieval scheme for video-on-demand systems. In particular, a zone-based data placement scheme is employed to reduce the average seek time of the disk array storage system and thus increase the disk access bandwidth to allow the video server provide more services of video programs concurrently. Furthermore, due to the inherent nature of video access, a popular program always requires more accesses and therefore occupies more disk I/O bandwidth as request for serving such program increases. A new retrieval strategy is proposed to maintain a single copy of each video program disregarding the popularity of the video programs, and to achieve maximum I/O throughput of the video server.

The high-resolution frequency estimators most commonly used, such as Least Square (LS) method based on AR model, MVSE, MUSIC and ESPRIT, determine estimates of the sinusoidal frequencies from the sample noise-corrupted data. In this paper, a new frequency estimation method named Pole-Placement Least Square (PPLS) is presented, which is a modified LS method with a certain number of model poles restricted to the unit circle. The statistical performance of PPLS is studied numerically, and compared with the Cramer-Rao bound as well as the statistical performance corresponding to the LS methods. PPLS is shown to have higher resolution than the conventional LS method. The relationship between poles location and its resolution is also discussed in detail.

The technique of replica placement has been extensively employed to improve client perceived performance and disperse server workload. In this paper, we study some well-known algorithms of replica placement on the network and observe the logarithmic relationship between replica number and total access cost. Numerous simulations are done and it is found that some replica algorithms obey the logarithmic relationship with high correlation coefficients. A logrithmic function is proposed about replica number and total access cost. The logarithmic relationship is applied to the minimum facility problem and a function is deduced to get the optimal replica number.

To sample a band-limited analog signal directly from the high frequency down to the baseband for the digital signal processing with significantly reduced computation, several concepts of the bandpass sampling are introduced. In this paper, a robust bandpass sampling scheme when there exist frequency deviations due to the channel effect and hardware instability is proposed for practical use, and the effects of the frequency deviations are discussed to select a proper sampling frequency.

The label placement problem is one of the most important problems in geographic information systems, cartography, graph drawing and graphical interface design. In this paper, we consider the problem of labeling points and curves in maps drawn from digital data. In digital maps, a curve is represented as a set of points and consists of many small segments. The label for each curve must be placed alongside the corresponding curve. We define a continuous labeling space for points and curves, and present an algorithm using this space for positioning labels. Computational results for subway and JR train maps in Tokyo are presented.

Buffer caching is an integral part of the operating system. In this paper, we propose a scheme that integrates buffer cache management and prefetching via cache partitioning. The scheme, which we call SA-W2R, is simple to implement, making it a feasible solution in real systems. In its basic form, for buffer replacement, it uses the LRU policy. However, its modular design allows for any replacement policy to be incorporated into the scheme. For prefetching, it uses the LRU-One Block Lookahead (LRU-OBL) approach, eliminating any extra burden that is generally necessary in other prefetching approaches. Implementation studies based on the GNU/Linux kernel version 2.2.14 show that the SA-W2R performs better than the scheme currently used, with a maximum increases of 23% for the workloads considered.

The problem of optimal placement of pilot symbols is considered for single carrier packet-based transmission over time varying channels. Both flat and frequency-selective fading channels are considered, and the time variation of the channel is modeled by Gauss-Markov process. The semi-blind linear minimum mean-square error (LMMSE) channel estimation is used. Two different performance criteria, namely the maximum mean square error (MSE) of the channel tap state over a packet and the cumulative channel MSE over a packet, are used to compare different placement schemes. The pilot symbols are assumed to be placed in clusters of length (2L+1) where L is the channel order, and only one non-zero training symbols is placed at the center of each cluster. It is shown that, at high SNR, either performance metric is minimized by distributing the pilot clusters throughout the packet periodically. It is shown that at low SNR, the placement is in fact not optimal. Finally, the performance under the periodic placement is compared with that obtained with superimposed pilots.

In this letter, base station placement is automatically determined from pre-defined candidate sites using a genetic approach, and the transmit power is obtained taking the interference situation into account in cases of interference-dominant systems. In order to apply a genetic algorithm to the base station placement problem, a real-valued representation scheme is proposed. Corresponding operators such as crossover and mutation are also introduced. The proposed algorithm is applied to an inhomogeneous traffic density environment, where a base station's coverage may be limited by offered traffic loads. An objective function is designed for performing the cell planning in a coverage- and cost-effective manner.

Many services on the Internet are provided by multiple identical servers in order to improve performance and robustness. The number, the location and the distribution of servers affect the performance and reliability of a service. The server placement is, however, often determined based on the empirical knowledge of the administrators. This paper investigates issues of the server placement in terms of the service performance and the server load. We identify that a server selection mechanism plays an important role in server placement, and thus, evaluate different server selection algorithms. The result shows that it is essential to the robustness of a service to employ a mechanism which distributes service requests to the servers according to the measured response time of each server. As a case study, we evaluate the server selection mechanisms employed by different DNS (Domain Name System) implementations. Then, we show the effects of the different server selection algorithms using root-server measurements taken at different locations around the world.

Using less wavelengths to serve more communication channels is one of the primary goals in the design of WDM networks. By installing wavelength converters at some nodes in a network, the number of wavelengths needed can be reduced. It has been observed that the more converters installed in a network, the less number of wavelengths is needed, given the same network load. In this paper, we study the relationship between the number of converters and the number of wavelengths needed in a system, and propose a suite of theories and results on how to place the minimal number of converters in the system so that the number of wavelengths W is at most a constant α times the maximal link load L (i.e., W α L), where α = 3/2 or 5/3. The results show a significant saving of converters in networks of both special topologies and general topology.

This paper describes a hybrid force-directed self-organizing neural network approach to printed circuit board (PCB) placement with consideration of electromagnetic compatibility (EMC). In most of the conventional PCB automatic placement algorithms, the only factor considered in the objective function is minimized total net length. However, for today's high speed and high density PCB, EMC compliance cannot be met by such single objective. To tackle this problem, the presented algorithm takes EMC into consideration, besides component overlap and minimized total net length. These factors are optimized by means of an adapted self-organizing map. Comparison of simulated placement results as well as actual measurements with commercial softwares confirms the effectiveness of the proposed method.

In optical networks, wavelength converters are required to improve the efficiency of wavelength-division multiplexing. In this paper, we propose a genetic algorithm to determine the optimal locations of the nodes in the network where a given number of converters are placed. Optimality is achieved by the minimum wavelength blocking probability. Our algorithm is applied to two realistic networks constructed from the locations of major cities in Ibaraki Prefecture and from those in Kanto District in Japan and is shown to reach the nearly optimal solution in a limited number of generations. The accuracy is verified by simulation. The computational time is compared with that of an exhaustive search algorithm.