Chip Multiprocessors (CMPs) allow different applications to share LLC (Last Level Cache). Since each application has different cache capacity demand, LLC capacity should be partitioned in accordance with the demands. Existing partitioning algorithms estimate the capacity demand of each core by stack processing considering the LRU (Least Recently Used) replacement policy only. However, anti-thrashing replacement algorithms like BIP (Binary Insertion Policy) and BIP-Bypass emerged to overcome the thrashing problem of LRU replacement policy in a working set greater than the available cache size. Since existing stack processing cannot estimate the capacity demand with anti-thrashing replacement policy, partitioning algorithms also cannot partition cache space with anti-thrashing replacement policy. In this letter, we prove that BIP replacement policy is not feasible to stack processing but BIP-bypass is. We modify stack processing to accommodate BIP-Bypass. In addition, we propose the pipelined hardware of modified stack processing. With this hardware, we can get the success function of the various capacities with anti-thrashing replacement policy and assess the cache capacity of shared cache adequate to each core in real time.

To improve Last-Level Cache (LLC) management, numerous approaches have been proposed requiring additional hardware budget and increased overhead. A number of these approaches even change the organization of the existing cache design. In this letter, we propose Adaptive Insertion and Promotion (AIP) policies based on Least Recently Used (LRU) replacement. AIP dynamically inserts a missed line in the middle of the cache list and promotes a reused line several steps left, realizing the combination of LRU and LFU policies deliberately under a single unified scheme. As a result, it benefits workloads with high locality as well as with many frequently reused lines. Most importantly, AIP requires no additional hardware other than a typical LRU list, thus it can be easily integrated into the existing hardware with minimal changes. Other issues around LLC such as scans, thrashing and dead lines are all explored in our study. Experimental results on the gem5 simulator with SPEC CUP2006 benchmarks indicate that AIP outperforms LRU replacement policy by an average of 5.8% on the misses per thousand instructions metric.

There exists a considerable number of node placement models and algorithms for simulation of wireless multihop networks. However, the topologies created with the existing algorithms do not have properties of real networks. We have developed NPART (Node Placement Algorithm for Realistic Topologies) in order to resolve this fundamental issue in simulation methodology. We compare topologies generated by NPART with open wireless multihop network in Berlin. The NPART generated topologies have almost identical node degree distribution, number of cut-edges and vertices as the real network. Unlike them, topologies generated with the common node placement models have their own characteristics which are considerably different both from NPART and from reality. NPART algorithm has been developed into a tool. We propose a method and present a tool for integration of NPART with various realistic node mobility algorithms and tools, such as Citymob [1] and MOVE [2]. This integrated tool allows easy and time-efficient generation of highly complex, realistic simulation scenarios. We use the tool to evaluate effects of integration between existing open community wireless multi-hop networks and vehicular ad-hoc networks (VANETs). The evaluation shows that despite partial coverage and peculiar topological properties of open networks, they offer high levels of performance and network availability to the mobile end users, virtually identical to performance and availability of planned, dedicatedly deployed networks. Our results indicate that the integration of these networks may bring considerable benefits to all parties involved.

We investigate a sparsely encoded Hopfield model with unit replacement by using a statistical mechanical method called self-consistent signal-to-noise analysis. We theoretically obtain a relation between the storage capacity and the number of replacement units for each sparseness a. Moreover, we compare the unit replacement model with the forgetting model in terms of the network storage capacity. The results show that the unit replacement model has a finite value of the optimal sparseness on an open interval 0 (1/2 coding) < a < 1 (the limit of sparseness) to maximize the storage capacity for a large number of replacement units, although the forgetting model does not.

Network-on-Chips (NoCs) have been proposed as a solution for addressing the global communication challenges in System-on-Chip (SoC) architectures that are implemented in nanoscale technologies. For the use of NoCs to be feasible in today's industrial designs, a custom-tailored, power- efficient NoC topology that satisfies the application characteristics is required. In this work, we present a design methodology that automates the synthesis of such application-specific NoC topologies. We present a method which integrates partitioning into floorplanning phase to explore optimal clustering of cores during floorplanning with minimized link and switch power consumption. Based on the size of applications, we also present an Integer Linear Programming and a heuristic method to place switches and network interfaces on the floorplan. Then, a power and timing aware path allocation algorithm is carried out to determine the connectivity across different switches. We perform experiments on several SoC benchmarks and present a comparison with the latest work. For small applications, the NoC topologies synthesized by our method show large improvements in power consumption (27.54%), hop-count (4%) and running time (66%) on average. And for large applications, the synthesized topologies result in large power (31.77%), hop-count (29%) and running time (94.18%) on average.

In this paper, we propose a placement and routing method for a new memory-based programmable logic device (MPLD) and confirm its capability by placing and routing benchmark circuits. An MPLD consists of multiple-output look-up tables (MLUTs) that can be used as logic and/or routing elements, whereas field programmable gate arrays (FPGAs) consist of LUTs (logic elements) and switch blocks (routing elements). MPLDs contain logic circuits more efficiently than FPGAs because of their flexibility and area efficiency. However, directly applying the existing placement and routing algorithms of FPGAs to MPLDs overcrowds the placed logic cells and causes a shortage of routing domains between logic cells. Our simulated annealing-based method considers the detailed wire congestion and nearness between logic cells based on the cost function and reserves the area for routing. In the experiments, our method reduced wire congestion and successfully placed and routed 27 out of 31 circuits, 13 of which could not be placed or routed using the versatile place and route tool (VPR), a well-known method for FPGAs.

The wear leveling is a critical factor which significantly impacts the lifetime and the performance of flash storage systems. To extend lifespan and reduce memory requirements, this paper proposed an efficient wear leveling without substantially increasing overhead and without modifying Flash Translation Layer (FTL) for huge-capacity flash storage systems, which is based on selective replacement. Experimental results show that our design levels the wear of different physical blocks with limited system overhead compared with previous algorithms.

WiMAX (IEEE 802.16) has emerged as a promising radio access technology for providing high speed broadband connectivity to subscribers over large geographic regions. New enhancements allow deployments of relay stations (RSs) that can extend the coverage of the base station (BS), increase cell capacity, or both. In this paper, we consider the placement of transparent RSs that maximize the cell capacity. We provide a closed-form approximation for the optimal location of RS inside a cell. A numerical analysis of a number of case studies validates the closed-form approximation. The numerical results show that the closed-form approximation is reasonably accurate.

In this letter, the reliabilty of the generalized normal-Laplace (GNL) distribution used for modeling the multiple access interference (MAI) plus noise in time-hopping (TH) binary phase-shift keying (BPSK) ultra-wideband (UWB) systems is evaluated in terms of the probability density function and the BER. The multiple access performance of TH-BPSK UWB systems based on GNL model is analyzed. The average BER performance obtained by using GNL approximation well matches with the exact BER results of TH-BPSK UWB systems. The parameter estimates of GNL distribution based on the moments estimation method is also presented.

This paper proposes a new method that reduces the computational cost of the phase-only correlation (POC)-based methods for displacement estimation in old film sequences. Conventional POC-based methods calculate all the points of the POC and only use the highest peak of the POC and its neighboring points to estimate the displacement with subpixel accuracy. Our proposed method reduces the computational cost by calculating the POC in a small region, instead of all the points of the POC. The proposed method combines a displacement pre-estimation with a modified inverse discrete Fourier transform (IDFT). The displacement pre-estimation uses the 1-D POCs of frame projections to pre-estimate the displacement with pixel accuracy and chooses a small region in the POC including the desired points for displacement estimation. The modified IDFT is then used to calculate the points in this small region for displacement estimation. Experimental results show that use of the proposed method can effectively reduce the computational cost of the POC-based methods without compromising the accuracy.

Previous research illustrates that LRU replacement policy is not efficient when applications exhibit a distant re-reference interval. Recently RRIP policy is proposed to improve the performance for such kind of workloads. However, the lack of access recency information in RRIP confuses the replacement policy to make the accurate prediction. To enhance the robustness of RRIP for recency-friendly workloads, we propose an Dynamic Adaptive Insertion and Re-reference Prediction (DAI-RRP) policy which evicts data based on both re-reference prediction value and the access recency information. DAI-RRP makes adaptive adjustment on insertion position and prediction value for different access patterns, which makes the policy robust across different workloads and different phases. Simulation results show that DAI-RRP outperforms LRU and RRIP. For a single-core processor with a 1 MB 16-way set last-level cache (LLC), DAI-RRP reduces CPI over LRU and Dynamic RRIP by an average of 8.1% and 2.7% respectively. Evaluations on quad-core CMP with a 4 MB shared LLC show that DAI-RRP outperforms LRU and Dynamic RRIP (DRRIP) on the weighted speedup metric by an average of 8.1% and 15.7% respectively. Furthermore, compared to LRU, DAI-RRP consumes the similar hardware for 16-way cache, or even less hardware for high-associativity cache. In summary, the proposed policy is practical and can be easily integrated into existing hardware approximations of LRU.

In the paper, a technique of the numerical inversion of multidimensional Laplace transforms (nD NILT), based on a complex Fourier series approximation is elaborated in light of a possible ralative error achievable. The detailed error analysis shows a relationship between the numerical integration of a multifold Bromwich integral and a complex Fourier series approximation, and leads to a novel formula relating the limiting relative error to the nD NILT technique parameters.

A novel computational method is proposed to investigate electromagnetic scattering problems. It is error controllable and reliable simulation in time domain can be performed. We apply the proposed method to analysis of transient scattering from open-ended structures and discuss scattering mechanisms.

Device mismatch plays an important role in the design of accurate analog circuits. The common centroid structure is commonly employed to reduce device mismatches caused by symmetrical layouts and processing gradients. Among the candidate placements generated by the common centroid approach, however, whichever achieves better matching is generally difficult to be determined without performing the time-consuming yield evaluation process. In addition, this rule-based methodology makes it difficult to achieve acceptable matching between multiple capacitors and to handle an irregular layout area. Based on a spatial correlation model, this study proposed a design methodology for yield enhancement of analog circuits using switched-capacitor techniques. An efficient and effective placement generator is developed to derive a placement for a circuit to achieve the highest or near highest correlation coefficient and thus accomplishing a better yield performance. A simple yield analysis is also developed to evaluate the achieved yield performance of a derived placement. Results show that the proposed methodology derives a placement which achieves better yield performance than those generated by the common centroid approach.

This paper presents a novel regularity evaluation of placement structure and techniques for handling conditional design rules along with dynamic diffusion sharing and well island generation, which are developed based on Sequence-Pair. The regular structures such as topological rows, arrays and repetitive structures are characterized by the way of forming sub-sequences of a sequence-pair. A placement objective is formulated balancing the regularity and the area efficiency. Furthermore, diffusion sharing and well island can be also identified looking into forming of a sequence-pair. In experiments, we applied our regularity-oriented placement mixed with the constraint-driven technique to real analog designs, and attained the results comparable to manual designs even when imposing symmetry constraints. Besides, the results also revealed the regularity serves to increase row-structures applicable to the diffusion sharing for area saving and wire-length reduction.

Secure channels can be realized by an authenticated key exchange (AKE) protocol that generates authenticated session keys between the involving parties. In, Shin et al., proposed a new kind of AKE (RSA-AKE) protocol whose goal is to provide high efficiency and security against leakage of stored secrets as much as possible. Let us consider more powerful attacks where an adversary completely controls the communications and the stored secrets (the latter is denoted by "replacement" attacks). In this paper, we first show that the RSA-AKE protocol is no longer secure against such an adversary. The main contributions of this paper are as follows: (1) we propose an RSA-based leakage-resilient AKE (RSA-AKE2) protocol that is secure against active attacks as well as replacement attacks; (2) we prove that the RSA-AKE2 protocol is secure against replacement attacks based on the number theory results; (3) we show that it is provably secure in the random oracle model, by showing the reduction to the RSA one-wayness, under an extended model that covers active attacks and replacement attacks; (4) in terms of efficiency, the RSA-AKE2 protocol is comparable to in the sense that the client needs to compute only one modular multiplication with pre-computation; and (5) we also discuss about extensions of the RSA-AKE2 protocol for several security properties (i.e., synchronization of stored secrets, privacy of client and solution to server compromise-impersonation attacks).

This paper considers replacement and maintenance policies for an operating unit which works at random times for jobs. The unit undergoes minimal repairs at failures and is replaced at a planned time T or at a number N of working times, whichever occurs first. The expected cost rate is obtained, and an optimal policy which minimizes it is derived analytically. The imperfect preventive maintenance (PM) model, where the unit is improved by PM after the completion of each working time, is analyzed. Furthermore, when the work of a job incurs some damage to the unit, the replacement model with number N is proposed. The expected cost rate is obtained by using theory of cumulative processes. Two modified models, where the unit is replaced at number N or at the first completion of the working time over time T, and it is replaced at T or number N, whichever occurs last, are also proposed. Finally, when the unit is replaced at time T, number N or Kth failure, whichever occurs first, the expected cost rate is also obtained.

This paper presents an efficient algorithm for incremental buffer insertion and module resizing for a full-placed floorplan. Our algorithm offers a method to use the white space in a given floorplan to resize modules and insert buffers, and at the same time keeps the resultant floorplan as close to the original one as possible. Both the buffer insertion and module resizing are modeled as geometric programming problems, and can be solved extremely efficiently using new developed solution methods. The experimental results suggest that the the wire length difference between the initial floorplan and result are quite small (less than 5%), and the global structure of the initial floorplan are preserved very well.

MEMS storage devices are new non-volatile secondary storages that have outstanding advantages over magnetic disks. MEMS storage devices, however, are much different from magnetic disks in the structure and access characteristics in the following ways. They have thousands of heads called probe tips and provide the following two major access facilities: (1) flexibility : freely selecting a set of probe tips for accessing data, (2) parallelism: simultaneously reading and writing data with the set of probe tips selected. Due to these characteristics, it is nontrivial to find data placements that fully utilize the capability of MEMS storage devices. In this paper, we propose a simple logical model called the Region-Sector (RS) model that abstracts major characteristics affecting data retrieval performance, such as flexibility and parallelism, from the physical MEMS storage model. We also suggest heuristic data placement strategies based on the RS model. To show the usability of the RS model, we derive new data placements for relational data and two-dimensional spatial data by using these strategies. Experimental results show that the proposed data placements improve the data retrieval performance by up to 4.7 times for relational data and by up to 18.7 times for two-dimensional spatial data of approximately 320 Mbytes compared with those of existing data placements. Further, these improvements are expected to be more marked as the database size grows.

How to minimize the number of mirroring resources under a QoS constraint (resource minimization problem) is an important issue in content delivery networks. This paper proposes a novel approach that takes advantage of the parallelism of dynamically reconfigurable processors (DRPs) to solve the resource minimization problem, which is NP-hard. Our proposal obtains the optimal solution by running an exhaustive search algorithm suitable for DRP. Greedy algorithms, which have been widely studied for tackling the resource minimization problem, cannot always obtain the optimal solution. The proposed method is implemented on an actual DRP and in experiments reduces the execution time by a factor of 40 compared to the conventional exhaustive search algorithm on a Pentium 4 (2.8 GHz).