Based on recent results for 2-D continuous-discrete systems, this paper develops 2-D Laplace-z transform, which can be used to analyze 2-D continuous-discrete signals and system in Laplace-z hybrid domain. Current 1-D Laplace transformation and z transform can be combined into the new 2-D s-z transform. However, 2-D s-z transformation is not a simple extension of 1-D transform, in 2-D case, we need consider the 2-D boundary conditions which don't occur in 1-D case. The hybrid 2-D definitions and theorems are given in the paper. To verify the results of this paper, we also derived a numerical inverse 2-D Laplace-z transform, applying it to show the 2-D pulse response of a stable 2-D continuous-discrete system.

The label placement problem is one of the most important problems in geographic information systems, cartography, graph drawing, and graphical interface design. In this paper, we considered the label size maximization problem for points with axes-parallel rectangular labels that correspond to character strings and have different widths based on the number of characters. We propose an algorithm for computing the optimum size for the label size maximization problem in the 2-position model and a polynomial time algorithm for the problem in the 4-position model. Our algorithm cannot obtain the maximum value in the 4-position model because the label size maximization problem in the 4-position model is NP-hard. However, our algorithm is efficient in practice, as shown by computational experiments. Further, computational results for JR trains, subways and major private railroads in Tokyo are presented.

Temperature-tracking is becoming of paramount importance in modern electronic design automation tools. In this paper, we present a deterministic thermal placement algorithm for standard cell based layout which can lead to a smooth temperature distribution over the die. It is mainly based on Fiduccia-Mattheyses partition scheme and a former substrate thermal model that can convert the known temperature constraints into the corresponding power distribution constraints. Moreover, a kind of force-directed heuristic based on cells' power consumption is introduced in the above process. Experimental results demonstrate a comparatively uniform temperature distribution and show a reduction of the maximal temperature on the die.

Displaced subdivision surface representation [13] is a new form of representing a polygonal surface model, where a detailed surface model is defined as a scaler-valued displacement map over a smooth domain surface; it puts forth a number of attractive features for editing, geometry compression, animation, scalability, and adaptive rendering of polygonal models. The construction of the smooth domain surface is a challenging task in the conversion process of a detailed polygonal surface model into this representation. In this paper, we propose a new efficient method for defining the smooth domain surface based on -subdivision scheme. The proposed algorithm not only performs better in terms of the quality of the generated surfaces but is computationally more efficient and occupies less memory as compared to the original algorithm [13] and generates surfaces with more levels of detail due to the specific nature of -subdivision when the prescribed target complexity of the generated mesh must not be exceeded. To corroborate the efficiency and the quality of the new technique, the conversion results for several public domain models have been presented.

This paper studies the problem of light splitter placement (LSP) and wavelength converter placement (WCP) in all-optical WDM networks to enable optimal provisioning of static and dynamic traffic through efficient photonic multicast connections. To solve the LSP-WCP problem under static traffic provisioning, an Integer Linear Programming model is formulated to achieve the optimal solution in the sense that the total number of wavelength channels required by the multicast requests is minimized. To solve the LSP-WCP problem under dynamic traffic provisioning, a complementary-combined LSP-WCP heuristic is proposed to minimize the multicast traffic blocking probability, and is proved through extensive simulations.

This paper presents two improved triple parity placement schemes, the HDD1 (Horizontal and Dual Diagonal) scheme and the HDD2 scheme, to enhance the reliability of a disk array system. Both the schemes can tolerate up to three column disk failures by using three types of parity information (horizontal, diagonal, and anti-diagonal parities) in a disk array. HDD1 scheme can decrease the frequency of bottlenecks because its horizontal and anti-diagonal parities are uniformly distributed over a disk array, with its diagonal parities placed in dedicated column disks. HDD2 scheme possesses one more column disks than HDD1 to store the horizontal parities and an additional diagonal parity; its anti-diagonal and diagonal parities are placed in the same way as in HDD1 scheme, only with a minor difference. The encoding and decoding algorithms of the two schemes are rather simple and straightforward, some steps of its procedure can even be executed in parallel, which makes the disk failure recovery faster.

This paper proposes a parity placement scheme, Row-Oblique Parity (ROP), for protecting against double disk failure in disk array systems. It stores all data unencoded, and uses only exclusive-or (XOR) operations to compute parity. ROP is provably optimal in computational complexity, both during construction and reconstruction. It is optimal in the capacity of redundant information stored and accessed. The simplicity of ROP allowed us to implement it within the current available RAID framework.

With VLSI design development, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated. In contrast to most of traditional works that handle this problem only in clock routing, we propose to navigate standard cell register placement to locations that enable further less clock routing wirelength and power. To minimize adverse impacts to conventional cell placement goals such as signal net wirelength and critical path delay, the register placement is carried out in the context of a quadratic placement. The proposed technique is particularly effective for the recently popular prescribed skew clock routing. Experiments on benchmark circuits show encouraging results.

The shuffle-like network (SL-Net) is known as a logical topology for WDM-based multihop packet-switched networks. Even if we fix the logical topology to an SL-Net, we can still reposition nodes in the SL-Net by re-tuning wavelengths of transmitters and/or receivers. In conventional node placement algorithms, routes between nodes are assumed to be given. In this paper, we propose two heuristic node placement algorithms for the SL-Net to decrease the average end-to-end packet transmission delay under a given traffic matrix in the case that routes are design variables. The principal idea is to prevent too many traffic flows from overlapping on any link. To attain the idea, in one of the algorithms, a node is selected one by one in a decreasing order of the sums of sending and receiving traffic requirements in nodes, and its placement and routes between the node and all the nodes already placed are simultaneously decided so that the maximum of the amounts of traffic on links at the moment is minimum. In the other algorithm, a node is selected in the same way, and first it is placed so that the average distance between the node and all the nodes already placed is as large as possible, and then routes between the node and all the nodes already placed are decided so that the maximum of the amounts of traffic on links at the moment is minimum. Numerical results for four typical traffic matrices show that either of the proposed algorithms has better performance than conventional algorithms for each matrix, and show that the proposed algorithms, which are based on a jointed optimization approach of node placement and routing, are superior to algorithms which execute node placement and routing as two isolated phases.

Incremental modification and optimization in VLSI physical design is of fundamental importance. Based on the O-tree (ordered tree) representation which has more prominent advantages in comparison with other topological representations of non-slicing floorplans, in this paper, we present an incremental placement algorithm for BBL (Building Block Layout) design in VLSI physical design. The good performance of experimental results in dealing with some instances proves the effectiveness of our algorithm.

This paper proposes flat and hierarchical approaches for generating a minimum-width transistor placement of CMOS cells in presence of non-dual P and N type transistors. Our approaches are the first exact method which can be applied to CMOS cells with any types of structure. Non-dual CMOS cells occupy a major part of an industrial standard-cell library. To generate the exact minimum-width transistor placement of non-dual CMOS cells, we formulate the transistor placement problem into Boolean Satisfiability (SAT) problem considering the P and N type transistors individually. Using the proposed method, the transistor placement problem of any types of CMOS cells can be solved exactly. In addition, the experimental results show that our flat approach generates smaller width placement for 29 out of 103 dual cells than that of the conventional method. Our hierarchical approach reduces the runtimes drastically. Although this approach has possibility to generate wider placements than that of the flat approach, the experimental results show that the width of only 3 out of 147 cells solved by our hierarchical approach are larger than that of the flat approach.

Interconnect Length Distribution (ILD) represents the correlation between the number of interconnects and their length. The ILD can predict power consumption, clock frequency, chip size, etc. High core utilization and small circuit area have been reported to improve chip performance. We propose an ILD model to predict the correlation between core utilization and chip performance. The proposed model predicts the influences of interconnect length and interconnect density on circuit performances. As core utilization increases, small and simple circuits improve the performances. In large complex circuits, decreasing the wire coupling capacitance is more important than decreasing the total interconnect length for improvement of chip performance. The proposed ILD model expresses the actual ILD more accurately than conventional models.

A timing-driven placement algorithm based on path topology analysis is presented. The optimization for path delay is transformed into cell location optimization. The algorithm pays much attention on path topologies and applies an effective force directed method to find cell target locations. Total wire length optimization is combined with the timing-driven placement algorithm. MCNC (Microelectronics Centre of North-Carolina) standard cell benchmarks are experimented and results show that our timing-driven placement algorithm can make the longest path delay improve up to 13% compared with wirelength driven placement.

This paper discusses how to minimize the number of dissection lines regarded as wiring channels on a floorplan corresponding to a placement of n modules. In a floorplan (rectangular dissection), the number of dissection lines exceeds the number of rooms exactly by three. Since a floorplan obtained from a given module placement may have many empty rooms where no module is assigned, redundant wiring channels and wire bends may also be generated. Hence, in order to reduce redundant channels and wire bends, removal of empty rooms is required. For this purpose, we formulate a problem of obtaining a floorplan with the minimum possible empty rooms based on a given module placement. Then, we propose a method of removing as many redundant empty rooms as possible by merging dissection lines on a floorplan in O(n) time. The number of empty rooms in the resultant floorplan is reduced to n- or less.

Nowadays more people have started using their mobile phone to access information they need from anywhere at anytime. In advanced mobile technology, Location Service allows users to quickly pinpoint their location as well as makes a recommendation to fascinating events. However, users desire more appropriate recommendation services. In other words, the message service should push a message at a proper place in time. In consequence, customers obtain a higher level of satisfaction. In this paper, we propose a framework of time, place, purpose and personal profile based recommendation service. We illustrate scenarios in "push", "pull" and "don't disturb" services, where our DB queries can recommend the relevant message to users. The three factors: time, place and purpose are mutually dependent and the basic rules to analyze the essential data are summarized. We also create algorithms for DB query. We are filtering messages by one important factor: personal profile such as user's preference and degree of preference. Furthermore, we discuss an implementation of the prototype system, including results of experimental evaluation.

Several regular topologies have been proposed to be used as the logical topology for WDM networks. These topologies are usually evaluated and compared based on the metrics related to network performance. It can be simply shown that this is generally not sufficient since better network performance can be achieved by increasing more network facilities. However, doing this eventually increases the network cost. Thus, the comparison of topologies must be performed by using an evaluation function that includes both the network performance metric and the network cost. In this paper, we propose a model to find the optimum regular logical topology for wavelength routed WDM networks. ShuffleNet, de Bruijn graph, hypercube, Manhattan Street Network, and GEMNet are the five well-known and commonly used regular topologies compared in this paper. By solving the two subproblems on node placement optimization, and routing and wavelength assignment, we obtain the evaluation function used in the topology comparison. Numerical results show that GEMNet is the optimum logical topology for the wavelength routed WDM networks, where it can take one of the three forms of ShuffleNet, de Bruijn graph, and its own configurations.

The performance of en-route web caching mainly depends on where the caches are located and how the cache contents are managed. In this paper, we address the problem of proxy placement in en-route web caching for tree networks, i.e., computing the optimal locations for placing k web proxies in a network such that some specified objectives are achieved. Based on our proposed model, we formulate this problem as an optimization problem and compute the optimal locations using a computationally efficient dynamic programming-based algorithm. We also extend our solution for tree networks to solve the same problem for autonomous systems. Finally, we implement our algorithms and evaluate our model on several performance metrics through extensive simulation experiments. We also compare the performance of our model with the best available heuristic KMPC model, as well as the random proxy placement model. The implementation results show that our model outperforms all the other models with respect to all performance metrics considered. The average improvements of our model over the KMPC model and the random proxy placement model are about 31.9 percent and 58.6 percent in terms of all the performance metrics considered.

Bandpass sampling algorithm is effectively adopted to obtain the digital signal with significantly reduced sampling rate for a single radio frequency(RF) signal. In order to apply the concept to multiple RF signals, we propose bandpass sampling algorithms with the normal and the inverse placements since we are interested in uniform order of the spectrum in digital domain after bandpass sampling. In addition, we verify the propose algorithms with generalized equation forms for the multiple RF signals.

Transient scattering from parallel plate waveguide cavities is studied by using the combination of a point matching technique and numerical inversion of Laplace transform. We thoroughly investigate the scattering mechanism for a half-sine pulse and modulated-sine pulse incidence. The advantages and disadvantages on the target recognition are clarified in terms of the internal objects, incident waveforms, and polarizations.

As audio and video applications have proliferated on the Internet, transcoding proxy caching has been considered as an important technique for improving network performance, especially for mobile networks. Due to several new emerging factors in the transcoding proxy, existing methods for proxy placement for web caching cannot be simply applied to solve the problem of proxy placement for transcoding proxy caching. This paper addresses the problem of proxy placement for coordinated en-route transcoding proxy caching for tree networks. We propose a model for this problem by including the new emerging factors in the transcoding proxy and present optimal solutions for this problem with/without constraints on the number of transcoding proxies using dynamic programming. Finally, we implement our algorithm and evaluate our model on various performance metrics through extensive simulation experiments. The implementation results show that our model outperforms the existing model for transcoding proxy placement for linear topology, as well as the random proxy placement model. The average improvements of our model over the other models are about 7.2 percent and 21.4 percent in terms of all the performance metrics considered.