Various reconfiguration schemes against faults of mesh-connected processor arrays have been proposed. As one of them, the mesh-connected processor arrays model based on single-track switches was proposed in [1]. The model has an advantage of its inherent simplicity of the routing hardware. Furthermore, the 2 track switch model [2] and the multiple track switch model [3] were proposed to enhance yields and reliabilities of arrays. However, in these models, Simplicity of the routing hardware is somewhat lost because multiple tracks are used for each row and column. In this paper, we present a builtin self-reconstruction approach for mesh-connected processor arrays which are partitioned into sub-arrays each using single-track switches. Spare PEs which are located on the boundaries of the sub-arrays compensate faulty PEs in these sub-arrays. First, we formulate a reconfigulation algorithm for partitioned mesh-arrays using a Hopfield-type neural network, and then its performance for reconfigulation in terms of survival rates and reliabilities of arrays and processing time are investigated by computer simulations. From the results, we can see that high reliabilites are achieved while processing time is a little and hardware overhead (links and switches) required for reconstruction is as same as that for the track switch model. Next, we present a hardware implementation of the neural algorithm so that a built-in self-reconfigurable scheme may be realized.

Many ATM switching modules with high performance have been proposed and analyzed. A development of a large scale ATM switching system (e.g., used as a central switch) is the key to realization of the broadband ISDN. However, the dimension of ATM switching ICs is limited by the technological and physical constraints on VLSI. A multistage switching configuration is one of the promising configurations for a large scale ATM switch. In this paper, we treat a 3-stage switching configuration with no internal bufferes; i.e., bufferless switches are employed at the first and second stages, and output buffered switches at the third stage. A short-term cell loss probability is analyzed in order to examine the influence of bursty traffic on performance of the bufferless switch used at the first two stages. Furthermore, we propose a 4-stage switching configuration with traffic distributors added at the first stage. This switch provides more paths between a pair of input and output ports than the 3-stage switching configuration mentioned above. A few schemes to distribute cells are compared. It is shown that the distributor successfully reduces the deterioration of cell loss probability due to bursty traffic by splitting incoming cells into several switching modules.

This paper proposes novel optical path accommodation design algorithms for networks wherein the number of wavelengths multiplexed into a fiber is restricted. This algorithm optimizes both optical path route and wavelength assignment in VWP/WP networks. It minimizes optical path cross-connect (OPXC) system scale in terms of incoming/outgoing fiber port numbers. A comparison in terms of required OPXC system scale between the WP and VWP schemes is demonstrated for the first time.

Time-frequency representations (TFRs) have been developed as tools for analysis of non-stationary signals. Signal dependent TFRs are known to perform well for a much wider range of signals than any fixed (signal independent) TFR. This paper describes customised and sequential versions of the signal dependent TFR proposed in [1]. The method, which is based on the use of the Radon transform at distance zero in the ambiguity domain, is simple and effective in dealing with both simulated and real data. The use of the described method for time-scale analysis is also presented. In addition, the paper investigates a simple technique for detection of noisy chirp signals using the Radon transfrom in the ambiguity domain.

This paper proposes a multi-fisheye distortion method which can show a large-scale telecommunication network in a single window on the display of a workstation or personal computer. This distortion method has three advantages over the conventional single-fisheye distortion method. First, the focus area is magnified smoothly by the fisheye distortion method, and the peripheral area coordinates are calculated linearly to avoid unnecessary distortion. Second, multiple focus areas are magnified smoothly by using an average of the coordinates calculated for the individual focuses. Third, the scale of unnecessary areas is reduced to provide sufficient space for magnification. The effectiveness of this method is demonstrated by applying to the display of large-scale networks. The effect of the resulting network map distortion on the user is tested by a subjective evaluation experiment.

Considering the trend towards adopting high efficiency picture coding schemes into digital broadcasting services, we investigate objective picture quality scales for evaluating digitally encoded still and moving pictures. First, the study on the objective picture quality scale for high definition still pictures coded by the JPEG scheme is summarized. This scale is derived from consideration of the following distortion factors; 1) weighted noise by the spatial frequency characteristics and masking effects of human vision, 2) block distortion, and 3) mosquito noise. Next, an objective picture quality scale for motion pictures of standard television coded by the hybrid DCT scheme is studied. In addition to the above distortion factors, the temporal frequency characteristics of vision are also considered. Furthermore, considering that all of these distortions vary over time in motion pictures, methods for determining a single objective picture quality value for this time varying distortion are examined. As a result, generally applicable objective picture quality scale is obtained that correlates extremely well with subjective picture quality scale for both still and motion pictures, irrespective of the contents of the pictures. Having an objective scale facilitates automated picture quality evaluation and control.

In this letter, we compare the three compound methods of the Multiple-scale technique to improve the quality of the scale values estimated by the method of fuzzy categories. The results show that the maximum compound method brings higher ability to estimate the scale values than the other methods despite categories used in the scale.

Scaling-down of MOSFETs (metal-oxide-semiconductor field effect transistors can be divided to semi-classical and quantum mechanical one. In the regime of semi-classical scaling-down the behavior of electrons and holes can be well described with the effective mass approximation and in the regime of quantum mechanical scaling-down the characteristics of electrons and holes as wave becomes markedly. The minimum size limit of MOSFETs scaled down in semi-classical regime is mainly determined by the subthreshold characteristics and the short channel effect on the threshold voltage and 0.1 µm will be the minimum channel length from practical viewpoints. Scaling down of MOSFETs enhances their operational speed, but the substrates with high resistivity which are often used in SOI (silicon on insulator) substrates result longer dielectric relaxation time. While the dielectric relaxation time becomes longer than the reciprocal of signal frequency, the semiconductors work as lossy dielectrics and may lead to new types of dynamic circuits. Modification of material properties utilizing the wave nature of electrons is an illustration of quantum mechanical way to improve characteristics of MOSFETs. Suppression of optical phonon scattering of two dimensional electrons by introducing two dimensional array of quantum dots into substrates is expected to improve high field characteristics of material. Brillouin zone folding is another way to control the band structure of materials, especially to make the indirect transition band structure to the direct transition band structure. Heat transfer from a chip severely limits the number of devices which can be integrated on the chip. Reduction of signal charge to electronic elementary charge, that is quantum limit, is expected to be useful for realization of nano-power electronics.

Robust-fault tolerance is a property that a computational result becomes nearly equal to the correct one at the occurrence of faults in digital system. There are many cases where the safety of digital control systems can be maintained if the property is satisfied. In this paper, robust-fault-tolerant three-valued arithmetic modules such as an adder and a multiplier are proposed. The positive and negative integers are represented by the number of 1's and 1's, respectively. The design concept of the arithmetic modules is that a fault makes linearly additive effect with a small value to the final result. Each arithmetic module consists of identical submodules linearly connected, so that multi-stage structure is formed to generate the final output from the last submodule. Between the input and output digits in the submodule some simple functional relation is satisfied with respect to the number of 1's and 1's. Moreover, the output digit value depends on very small portion of the submodules including the input digits. These properties make the linearly additive effect with a small value to the final result in the arithmetic modules even if multiple faults are occurred at the input and output of any gates in the submodules. Not only direct three-valued representation but also the use of three-valued logic circuits is inherently suitable for efficient implementation of the arithmetic VLSI system. The evaluation of the robust-fault-tolerant three-valued arithmetic modules is done with regard to the chip size and the speed using the standard CMOS design rule. As a result, it is made clear that the chip size can be greatly reduced.

Fabrication of 0.2 to 0.3 µm features is vital for future ultralarge scale integration devices. An area of particular concern is whether optical lithography can delineate such feature sizes, i.e., less than the exposure wavelength. The use of a phase shift mask is one of the most effective means of improving resolution in optical lithography. This technology basically makes use of the interference between light transmitting through adjacent apertures of the mask. Various types of phase shift masks and their imaging characteristics are discussed and compared with conventional normal transmission masks. To apply these masks effectively to practical patterns, a phase shifter pattern design tool and mask repair method must be established. The phase shifting technology offers a potential to fabricate 0.3 µm features by using the current i-line stepper, and 0.2 µm features by using excimer laser stepper.

A new design method is proposed for realizing a hypercube network (HC) structured multicomputer system on a wafer using wafer-scale integration (WSI). The probability that an HC can be constructed on a wafer is higher in this method than in the conventional method; this probavility is called a construction probability. We adopt the FUSS method for the processor (PE) address allocation in our desing because it has a high success probability in the allocation. Even if the design renders the address allocation success probalility hegher, it is of no use if it makes either the maximum wiring length between PEs or the array size (wiring area) larger. A new wiring channel structure capable of connecting PEs on a wafer is proposed in this paper, where a channel, called a basic channel, is used. A one-dimensional-array sub-HC row network (RN) or column networks (CN) can be constructed using the basic channel. The sub-HC construction method, which embeds wirings into the basic channel, is also proposed. It requires almost the same wiring width as conventional method. However, it has an advantage in that maximum wiring length between PEs can be about half that of the conventional method. If PEs must be shifted in the case of PE defects, they can be shifted and connected to the basic channel using other PE shifting channels, and an RN or CN can be constructed. The maximum wiring length between PEs, array size, and construction probability will also be derived, and it will be shown that the proposed design is superior to the conventional one.

High frequency and low power 128/129 dual modulus prescaler ICs are developed for mobile communication applications, using 0.5 µm GaAs MESFET technology. Provided with an on-chip voltage regulator, a prescaler IC with an input amplifier operates in a wide frequency range from 200 MHz to 1,500 MHz at input power from -15 dBm to +17 dBm at the temperature of -30 to +120 with supply voltage of 2.7 V, 3.0 V and 5.0 V. At the same time, it demonstrated its low power characteristics consuming 3.68 mA with 3.0 V at +30 in operation, 0.16 mA while powered-off. Another prescaler IC without an input amplifier operates up to 1,650 MHz with Vdd=2.7 V, 3.0 V and 5.0 V at +30, dissipating 2.74 mA/3.0 V.