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[Keyword] scale(272hit)

101-120hit(272hit)

  • SAFE: A Scalable Autonomous Fault-Tolerant Ethernet Scheme for Large-Scale Star Networks

    Dong Ho LEE  You-Ze CHO  Hoang-Anh PHAM  Jong Myung RHEE  Yeonseung RYU  

     
    PAPER-Network

      Vol:
    E95-B No:10
      Page(s):
    3158-3167

    In this paper, we present a new fault-tolerant, large-scale star network scheme called Scalable Autonomous Fault-tolerant Ethernet (SAFE). The primary goal of a SAFE scheme is to provide network scalability and autonomous fault detection and recovery. SAFE divides a large-scale, mission-critical network, such as the naval combatant network, into several subnets by limiting the number of nodes in each subnet. This network can be easily configured as a star network in order to meet fault recovery time requirements. For SAFE, we developed a novel mechanism for inter-subnet fault detection and recovery; a conventional Ethernet-based heartbeat mechanism is used in each subnet. Theoretical and experimental performance analyses of SAFE in terms of fail-over time were conducted under various network failure scenarios. The results validate our scheme.

  • Event Information Based Optimal Sensor Deployment for Large-Scale Wireless Sensor Networks

    Yunbum CHOI  Ikram SYED  Hoon KIM  

     
    LETTER-Network

      Vol:
    E95-B No:9
      Page(s):
    2944-2947

    Sensor deployment to achieve better system performance is one of the critical issues in wireless sensor networks (WSN). This letter proposes an effective sensor deployment scheme for large area sensor networks, where the event occurrence rate varies over the sensor-deployed region. Based on local event occurrence rate, the proposed scheme determines the number of sensors that should be deployed in each local region to maximize the overall detection probability. Simulation results show that the sensor deployment by the proposed scheme improves detection capability by 21% in comparison to the Incidence algorithm.

  • Analyzing and Reducing the Impact of Traffic on Large-Scale NAT

    Ryoichi KAWAHARA  Tatsuya MORI  Takeshi YADA  Noriaki KAMIYAMA  

     
    PAPER-Network

      Vol:
    E95-B No:9
      Page(s):
    2815-2827

    We investigate the impact of traffic on the performance of large-scale NAT (LSN), since it has been attracting attention as a means of better utilizing the limited number of global IPv4 addresses. We focus on the number of active flows because they drive up the LSN memory requirements in two ways; more flows must be held in LSN memory, and more global IPv4 addresses must be prepared. Through traffic measurement data analysis, we found that more than 1% of hosts generated more than 100 TCP flows or 486 UDP flows at the same time, and on average, there were 1.43-3.99 active TCP flows per host, when the inactive timer used to clear the flow state from a flow table was set to 15 s. When the timer is changed from 15 s to 10 min, the number of active flows increases more than tenfold. We also investigate how to reduce the above impact on LSN in terms of saving memory space and accommodating more users for each global IPv4 address. We show that to save memory space, regulating network anomalies can reduce the number of active TCP flows on an LSN by a maximum of 48.3% and by 29.6% on average. We also discuss the applicability of a batch flow-arrival model for estimating the variation in the number of active flows, when taking into account that the variation is needed to prepare an appropriate memory space. One way to allow each global IPv4 address to accommodate more users is to better utilize destination IP address information when mapping a source IP address from a private address to a global IPv4 address. This can effectively reduce the required number of global IPv4 addresses by 85.9% for TCP traffic and 91.9% for UDP traffic on average.

  • Parallel Dual Modulus Prescaler with a Step Size of 0.5

    Hideyuki NAKAMIZO  Kenichi TAJIMA  Ryoji HAYASHI  Kenji KAWAKAMI  Toshiya UOZUMI  

     
    PAPER

      Vol:
    E95-C No:7
      Page(s):
    1189-1194

    This paper shows a new pulse swallow programmable frequency divider with the division step size of 0.5. To realize the division step size of 0.5 by a conventional pulse swallow method, we propose a parallel dual modulus prescaler with the division ratio of P and P + 0.5. It consists of simple circuit elements and has an advantage over the conventional dual modulus prescaler with the division step size of 0.5 in high frequency operation. The proposed parallel dual modulus prescaler with the division ratio 8 and 8.5 is implemented in the 0.13-µm CMOS technology. The proposed architecture achieves 7 times higher frequency operation than the conventional one theoretically. It is verified the functions over 5 GHz.

  • Scalable Virtual Network Mapping Algorithm for Internet-Scale Networks

    Qiang YANG  Chunming WU  Min ZHANG  

     
    PAPER

      Vol:
    E95-B No:7
      Page(s):
    2222-2231

    The proper allocation of network resources from a common physical substrate to a set of virtual networks (VNs) is one of the key technical challenges of network virtualization. While a variety of state-of-the-art algorithms have been proposed in an attempt to address this issue from different facets, the challenge still remains in the context of large-scale networks as the existing solutions mainly perform in a centralized manner which requires maintaining the overall and up-to-date information of the underlying substrate network. This implies the restricted scalability and computational efficiency when the network scale becomes large. This paper tackles the virtual network mapping problem and proposes a novel hierarchical algorithm in conjunction with a substrate network decomposition approach. By appropriately transforming the underlying substrate network into a collection of sub-networks, the hierarchical virtual network mapping algorithm can be carried out through a global virtual network mapping algorithm (GVNMA) and a local virtual network mapping algorithm (LVNMA) operated in the network central server and within individual sub-networks respectively with their cooperation and coordination as necessary. The proposed algorithm is assessed against the centralized approaches through a set of numerical simulation experiments for a range of network scenarios. The results show that the proposed hierarchical approach can be about 5-20 times faster for VN mapping tasks than conventional centralized approaches with acceptable communication overhead between GVNCA and LVNCA for all examined networks, whilst performs almost as well as the centralized solutions.

  • A 1-V TSPC Dual Modulus Prescaler with Speed Scalability Using Forward Body Biasing in 0.18 µm CMOS

    Hyunchol SHIN  

     
    BRIEF PAPER-Electronic Circuits

      Vol:
    E95-C No:6
      Page(s):
    1121-1124

    The operating speed scalability is demonstrated by using the forward body biasing method for a 1-V 0.18-µm CMOS true single-phase clocking (TSPC) dual-modulus prescaler. With the forward body bias voltage varying between 0 and 0.4 V, the maximum operating speed changes by about 40–50% and the maximum input sensitivity frequency changes by about 400%. This speed scalability is achieved with less than 0.5-dB phase noise degradation. This demonstration indicates that the forward body biasing method is instrumental to build a cost-saving power-efficient 1-V 0.18-µm CMOS radio for low-power WBAN and WSN applications.

  • Using a Renormalization Group to Create Ideal Hierarchical Network Architecture with Time Scale Dependency Open Access

    Masaki AIDA  

     
    INVITED PAPER

      Vol:
    E95-B No:5
      Page(s):
    1488-1500

    This paper employs the nature-inspired approach to investigate the ideal architecture of communication networks as large-scale and complex systems. Conventional architectures are hierarchical with respect to the functions of network operations due entirely to implementation concerns and not to any fundamental conceptual benefit. In contrast, the large-scale systems found in nature are hierarchical and demonstrate orderly behavior due to their space/time scale dependencies. In this paper, by examining the fundamental requirements inherent in controlling network operations, we clarify the hierarchical structure of network operations with respect to time scale. We also describe an attempt to build a new network architecture based on the structure. In addition, as an example of the hierarchical structure, we apply the quasi-static approach to describe user-system interaction, and we describe a hierarchy model developed on the renormalization group approach.

  • Performance of Thorup's Shortest Path Algorithm for Large-Scale Network Simulation

    Yusuke SAKUMOTO  Hiroyuki OHSAKI  Makoto IMASE  

     
    PAPER-Fundamental Theories for Communications

      Vol:
    E95-B No:5
      Page(s):
    1592-1601

    In this paper, we investigate the performance of Thorup's algorithm by comparing it to Dijkstra's algorithm for large-scale network simulations. One of the challenges toward the realization of large-scale network simulations is the efficient execution to find shortest paths in a graph with N vertices and M edges. The time complexity for solving a single-source shortest path (SSSP) problem with Dijkstra's algorithm with a binary heap (DIJKSTRA-BH) is O((M + N) log N). An sophisticated algorithm called Thorup's algorithm has been proposed. The original version of Thorup's algorithm (THORUP-FR) has the time complexity of O(M + N). A simplified version of Thorup's algorithm (THORUP-KL) has the time complexity of O(M α(N) + N) where α(N) is the functional inverse of the Ackerman function. In this paper, we compare the performances (i.e., execution time and memory consumption) of THORUP-KL and DIJKSTRA-BH since it is known that THORUP-FR is at least ten times slower than Dijkstra's algorithm with a Fibonaccii heap. We find that (1) THORUP-KL is almost always faster than DIJKSTRA-BH for large-scale network simulations, and (2) the performances of THORUP-KL and DIJKSTRA-BH deviate from their time complexities due to the presence of the memory cache in the microprocessor.

  • Design of a Tree-Queue Model for a Large-Scale System

    Byungsung PARK  Jaeyeong YOO  Hagbae KIM  

     
    LETTER-Dependable Computing

      Vol:
    E95-D No:4
      Page(s):
    1159-1161

    In a large queuing system, the effect of the ratio of the filled data on the queue and waiting time from the head of a queue to the service gate are important factors for process efficiency because they are too large to ignore. However, many research works assumed that the factors can be considered to be negligible according to the queuing theory. Thus, the existing queuing models are not applicable to the design of large-scale systems. Such a system could be used as a product classification center for a home delivery service. In this paper, we propose a tree-queue model for large-scale systems that is more adaptive to efficient processes compared to existing models. We analyze and design a mean waiting time equation related to the ratio of the filled data in the queue. Based on simulations, the proposed model demonstrated improvement in process-efficiency, and it is more suitable to realistic system modeling than other compared models for large-scale systems.

  • Modeling and Analysis of Substrate Noise Coupling in Analog and RF ICs

    Makoto NAGATA  

     
    INVITED PAPER

      Vol:
    E95-A No:2
      Page(s):
    430-438

    Substrate noise coupling has been seriously concerned in the design of advanced analog and radio frequency (RF) integrated circuits (ICs). This paper reviews recent advancements in the modeling, analysis, and evaluation of substrate noise coupling at IC chip level. Noise generation from digital circuits and propagation to the area of analog circuits are clearly visualized both by full-chip simulation as well as by on-chip measurements, for silicon test vehicles. The impacts of substrate noise coupling are also in-depth discussed at device, circuit, as well as system levels. Overall understanding of substrate noise coupling will then provide the basics for highly reliable design of analog and RF ICs.

  • Robust Tracking Using Particle Filter with a Hybrid Feature

    Xinyue ZHAO  Yutaka SATOH  Hidenori TAKAUJI  Shun'ichi KANEKO  

     
    PAPER-Image Recognition, Computer Vision

      Vol:
    E95-D No:2
      Page(s):
    646-657

    This paper presents a novel method for robust object tracking in video sequences using a hybrid feature-based observation model in a particle filtering framework. An ideal observation model should have both high ability to accurately distinguish objects from the background and high reliability to identify the detected objects. Traditional features are better at solving the former problem but weak in solving the latter one. To overcome that, we adopt a robust and dynamic feature called Grayscale Arranging Pairs (GAP), which has high discriminative ability even under conditions of severe illumination variation and dynamic background elements. Together with the GAP feature, we also adopt the color histogram feature in order to take advantage of traditional features in resolving the first problem. At the same time, an efficient and simple integration method is used to combine the GAP feature with color information. Comparative experiments demonstrate that object tracking with our integrated features performs well even when objects go across complex backgrounds.

  • A Basic Fuzzy-Estimation Theory for Available Operation of Extremely Complicated Large-Scale Network Systems

    Kazuo HORIUCHI  

     
    PAPER-Circuit Theory

      Vol:
    E95-A No:1
      Page(s):
    338-345

    In this paper, we shall describe a basic fuzzy-estimation theory based on the concept of set-valued operators, suitable for available operation of extremely complicated large-scale network systems. Fundamental conditions for availability of system behaviors of such network systems are clarified in a form of β-level fixed point theorem for system of fuzzy-set-valued operators. Here, the proof of this theorem is accomplished by the concept of Hausdorff's ball measure of non-compactness introduced into the Banach space.

  • On Structural Analysis and Efficiency for Graph-Based Rewiring Techniques

    Fu-Shing CHIM  Tak-Kei LAM  Yu-Liang WU  Hongbing FAN  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E94-A No:12
      Page(s):
    2853-2865

    The digital logic rewiring technique has been shown to be one of the most powerful logic transformation methods. It has been proven that rewiring is able to further improve some already excellent results on many EDA problems, ranging from logic minimization, partitioning, FPGA technology mappings to final routings. Previous studies have shown that ATPG-based rewiring is one of the most powerful tools for logic perturbation while a graph-based rewiring engine is able to cover nearly one fifth of the target wires with 50 times runtime speedup. For some problems that only require good-enough and very quick solutions, this new rewiring technique may serve as a useful and more practical alternative. In this work, essential elements in graph-based rewiring such as rewiring patterns, pattern size and locality, etc., have been studied to understand their relationship with rewiring performance. A structural analysis on the target-alternative wire pairs discovered by ATPG-based and graph-based engines has also been conducted to analyze the structural characteristics that favor the identification of alternative wires. We have also developed a hybrid rewiring approach that can take the advantages from both ATPG-based and graph-based rewiring. Experimental results suggest that our hybrid engine is able to achieve about 50% of alternative wire coverage when compared with the state-of-the-art ATPG-based rewiring engine with only 4% of the runtime. Through applying our hybrid rewiring approach to the FGPA technology mapping problem, we could achieve similar depth level and look-up table number reductions with much shorter runtime. This shows that the fast runtime of our hybrid approach does not sacrifice the quality of certain rewiring applications.

  • Matching Handwritten Line Drawings with Von Mises Distributions

    Katsutoshi UEAOKI  Kazunori IWATA  Nobuo SUEMATSU  Akira HAYASHI  

     
    PAPER-Pattern Recognition

      Vol:
    E94-D No:12
      Page(s):
    2487-2494

    A two-dimensional shape is generally represented with line drawings or object contours in a digital image. Shapes can be divided into two types, namely ordered and unordered shapes. An ordered shape is an ordered set of points, while an unordered shape is an unordered set. As a result, each type typically uses different attributes to define the local descriptors involved in representing the local distributions of points sampled from the shape. Throughout this paper, we focus on unordered shapes. Since most local descriptors of unordered shapes are not scale-invariant, we usually make the shapes in an image data set the same size through scale normalization, before applying shape matching procedures. Shapes obtained through scale normalization are suitable for such descriptors if the original whole shapes are similar. However, they are not suitable if parts of each original shape are drawn using different scales. Thus, in this paper, we present a scale-invariant descriptor constructed by von Mises distributions to deal with such shapes. Since this descriptor has the merits of being both scale-invariant and a probability distribution, it does not require scale normalization and can employ an arbitrary measure of probability distributions in matching shape points. In experiments on shape matching and retrieval, we show the effectiveness of our descriptor, compared to several conventional descriptors.

  • High-Speed and Low-Complexity Decoding Architecture for Double Binary Turbo Code

    Kon-Woo KWON  Kwang-Hyun BAEK  Jeong Woo LEE  

     
    LETTER-VLSI Design Technology and CAD

      Vol:
    E94-A No:11
      Page(s):
    2458-2461

    We propose a high-speed and low-complexity architecture for the very large-scale integration (VLSI) implementation of the maximum a posteriori probability (MAP) algorithm suited to the double binary turbo decoder. For this purpose, equation manipulations on the conventional Linear-Log-MAP algorithm and architectural optimization are proposed. It is shown by synthesized simulations that the proposed architecture improves speed, area and power compared with the state-of-the-art Linear-Log-MAP architecture. It is also observed that the proposed architecture shows good overall performance in terms of error correction capability as well as decoder hardware's speed, complexity and throughput.

  • Scalable Object Discovery: A Hash-Based Approach to Clustering Co-occurring Visual Words

    Gibran FUENTES PINEDA  Hisashi KOGA  Toshinori WATANABE  

     
    PAPER-Image Recognition, Computer Vision

      Vol:
    E94-D No:10
      Page(s):
    2024-2035

    We present a scalable approach to automatically discovering particular objects (as opposed to object categories) from a set of images. The basic idea is to search for local image features that consistently appear in the same images under the assumption that such co-occurring features underlie the same object. We first represent each image in the set as a set of visual words (vector quantized local image features) and construct an inverted file to memorize the set of images in which each visual word appears. Then, our object discovery method proceeds by searching the inverted file and extracting visual word sets whose elements tend to appear in the same images; such visual word sets are called co-occurring word sets. Because of unstable and polysemous visual words, a co-occurring word set typically represents only a part of an object. We observe that co-occurring word sets associated with the same object often share many visual words with one another. Hence, to obtain the object models, we further cluster highly overlapping co-occurring word sets in an agglomerative manner. Remarkably, we accelerate both extraction and clustering of co-occurring word sets by Min-Hashing. We show that the models generated by our method can effectively discriminate particular objects. We demonstrate our method on the Oxford buildings dataset. In a quantitative evaluation using a set of ground truth landmarks, our method achieved higher scores than the state-of-the-art methods.

  • Automatic Scale Detection for Contour Fragment Based on Difference of Curvature

    Kei KAWAMURA  Daisuke ISHII  Hiroshi WATANABE  

     
    PAPER-Pattern Recognition

      Vol:
    E94-D No:10
      Page(s):
    1998-2005

    Scale-invariant features are widely used for image retrieval and shape classification. The curvature of a planar curve is a fundamental feature and it is geometrically invariant with respect it the coordinate system. The curvature-based feature varies in position when multi-scale analysis is performed. Therefore, it is important to recognize the scale in order to detect the feature point. Numerous shape descriptors based on contour shapes have been developed in the field of pattern recognition and computer vision. A curvature scale-space (CSS) representation cannot be applied to a contour fragment and requires the tracking of feature points. In a gradient-based curvature computation, although the gradient computation considers the scale, the curvature is normalized with respect to not the scale but the contour length. The scale-invariant feature transform algorithm that detects feature points from an image solves similar problems by using the difference of Gaussian (DoG). It is difficult to apply the SIFT algorithm to a planar curve for feature extraction. In this paper, an automatic scale detection method for a contour fragment is proposed. The proposed method detects the appropriate scales and their positions on the basis of the difference of curvature (DoC) without the tracking of feature points. To calculate the differences, scale-normalized curvature is introduced. An advantage of the DoC algorithm is that the appropriate scale can be obtained from a contour fragment as a local feature. It then extends the application area. The validity of the proposed method is confirmed by experiments. The proposed method provides the most stable and robust scales of feature points among conventional methods such as curvature scale-space and gradient-based curvature.

  • ROCKET: A Robust Parallel Algorithm for Clustering Large-Scale Transaction Databases

    Woong-Kee LOH  Yang-Sae MOON  Heejune AHN  

     
    LETTER-Artificial Intelligence, Data Mining

      Vol:
    E94-D No:10
      Page(s):
    2048-2051

    We propose a robust and efficient algorithm called ROCKET for clustering large-scale transaction databases. ROCKET is a divisive hierarchical algorithm that makes the most of recent hardware architecture. ROCKET handles the cases with the small and the large number of similar transaction pairs separately and efficiently. Through experiments, we show that ROCKET achieves high-quality clustering with a dramatic performance improvement.

  • Image Categorization Using Scene-Context Scale Based on Random Forests

    Yousun KANG  Hiroshi NAGAHASHI  Akihiro SUGIMOTO  

     
    PAPER-Image Recognition, Computer Vision

      Vol:
    E94-D No:9
      Page(s):
    1809-1816

    Scene-context plays an important role in scene analysis and object recognition. Among various sources of scene-context, we focus on scene-context scale, which means the effective scale of local context to classify an image pixel in a scene. This paper presents random forests based image categorization using the scene-context scale. The proposed method uses random forests, which are ensembles of randomized decision trees. Since the random forests are extremely fast in both training and testing, it is possible to perform classification, clustering and regression in real time. We train multi-scale texton forests which efficiently provide both a hierarchical clustering into semantic textons and local classification in various scale levels. The scene-context scale can be estimated by the entropy of the leaf node in the multi-scale texton forests. For image categorization, we combine the classified category distributions in each scale and the estimated scene-context scale. We evaluate on the MSRC21 segmentation dataset and find that the use of the scene-context scale improves image categorization performance. Our results have outperformed the state-of-the-art in image categorization accuracy.

  • Assessing the Impact of Node Churn to Random Walk-Based Overlay Construction

    Kyungbaek KIM  

     
    LETTER-Information Network

      Vol:
    E94-D No:9
      Page(s):
    1830-1833

    Distributed systems desire to construct a random overlay graph for robustness, efficient information dissemination and load balancing. A random walk-based overlay construction is a promising alternative to generate an ideal random scale free overlay in distributed systems. However, a simple random walk-based overlay construction can be affected by node churn. Especially, the number of edges increases and the degree distribution is skewed. This inappropriate distortion can be exploited by malicious nodes. In this paper, we propose a modified random walk-based overlay construction supported by a logistic/trial based decision function to compensate the impact of node churn. Through event-driven simulations, we show that the decision function helps an overlay maintain the proper degree distribution, low diameter and low clustering coefficient with shorter random walks.

101-120hit(272hit)