This paper proposes high-Q distributed constant passive devices using wafer-level chip scale package (WL-CSP) technology, which can be realized on a Si CMOS chip. A 90directional coupler using the WL-CSP technology has center frequency of 25.6 GHz, insertion loss of -0.5 dB and isolation of -29.8 dB in the measurement result. The WL-CSP technology contributes to realize low-loss RF passive devices on Si CMOS chip, which is indispensable to achieve small-size, cost-effective and low-power monolithic wireless communication circuits (MWCCs).

Digital watermarking is a technique that aims at hiding a message signal in a multimedia signal for copyright claim, authentication, device control, or broadcast monitoring, etc. In this paper, we focus on embedding watermarks into still images, where the watermarks themselves can be binary sequences or grayscale images. We propose to scramble the watermark bits with pseudo-noise (PN) or orthogonal codes before they are embedded into an image. We also try to incorporate error correction coding (ECC) into the watermarking scheme, anticipating reduction of the watermark bit error rate (WBER). Due to the similarity between the PN/orthogonal-coded watermarking and the spread spectrum communication, it is natural that, following similar derivations regarding data BER in digital communications, we derive certain explicit quantitative relationships regarding the tradeoff between the WBER, the watermark capacity (i.e. the number of watermark bits) and the distortion suffered by the original image, which is measured in terms of the embedded image's signal-to-noise ratio (abbreviated as ISNR). These quantitative relationships are compactly summarized into a so-called tradeoff triangle, which constitutes the major contribution of this paper. For the embedding of grayscale watermarks, an unequal error protection (UEP) scheme is proposed to provide different degrees of robustness for watermark bits of different degrees of significance. In this UEP scheme, optimal strength factors for embedding different watermark bits are sought so that the mean squared error suffered by the extracted watermark, which is by itself a grayscale image, is minimized while a specified ISNR is maintained.

In this paper, we shall describe about a refined theory based on the concept of set-valued operators, suitable for available operation of extremely complicated large-scale network systems. The deduction of theory is accomplished in a weak topology introduced into the Banach space. Fundamental conditions for availability of system behaviors of such network systems are clarified, as a result, in a form of fixed point theorem for system of set-valued operators.

Several research fields have to deal with very large classification problems, e.g. handwritten character recognition and speech recognition. Many works have proposed methods to address problems with large number of samples, but few works have been done concerning problems with large numbers of classes. CombNET-II was one of the first methods proposed for such a kind of task. It consists of a sequential clustering VQ based gating network (stem network) and several Multilayer Perceptron (MLP) based expert classifiers (branch networks). With the objectives of increasing the classification accuracy and providing a more flexible model, this paper proposes a new model based on the CombNET-II structure, the CombNET-III. The new model, intended for, but not limited to, problems with large number of classes, replaces the branch networks MLP with multiclass Support Vector Machines (SVM). It also introduces a new probabilistic framework that outputs posterior class probabilities, enabling the model to be applied in different scenarios (e.g. together with Hidden Markov Models). These changes permit the use of a larger number of smaller clusters, which reduce the complexity of the final classifiers. Moreover, the use of binary SVM with probabilistic outputs and a probabilistic decoding scheme permit the use of a pairwise output encoding on the branch networks, which reduces the computational complexity of the training stage. The experimental results show that the proposed model outperforms both the previous model CombNET-II and a single multiclass SVM, while presenting considerably smaller complexity than the latter. It is also confirmed that CombNET-III classification accuracy scales better with the increasing number of clusters, in comparison with CombNET-II.

Numerous studies have shown that scaling exponents of internet traffic change over time or scaling ranges. In order to analyze long-range dependent traffic with changing scaling exponents over time scales, we propose a multi-scale traffic model that incorporates the notion of a piecewise self-similar process, a process with spectral changes on its scaling behavior. We can obtain a performance curve smoothened over the range of queue length corresponding to time scales with different scaling exponents by adopting multiple self-similar processes piecewise into different spectra of time scale. The analytical method for the multiscale fractional Brownian motion is discussed as a model for this approach. A comparison of the analytical and simulation results, using traffic data obtained from backbone networks, shows that our model provides a good approximation for Gaussian traffic.

Four 50% duty-cycle divide-by-3 prescalers--positively/ negatively triggered sample-sample-hold (SSH) and sample-hold-hold (SHH) prescalers--are designed based on the current switchable D flip-flops and discussed in this paper. The positively triggered SSH and SHH prescalers are fabricated using the 0.35-µm SiGe BiCMOS technology and measured by the real-time oscilloscope and the spectrum analyzer. The SHH prescaler is our proposed structure and demonstrated in this paper. According to the measurement results, under the condition of the same input power, its maximum operation frequency is twice as high as that of the SSH prescaler thanks to better signal synchronization. At 2.7 V supply, the SSH prescaler operates from 500 MHz to 2 GHz as the SHH prescaler performs from 1 GHz to 3.4 GHz. The input sensitivity level of both structures is about -5 dBm, while the maximum output power is also about -5 dBm. The core current consumption is 4.538 mA and 4.258 mA for the SSH and SHH prescalers, respectively.

The operation of analog circuits from ultra low supply voltages becomes necessary due to semiconductor technology scaling. Yet traditional design techniques cannot be used. In this paper, we review techniques that allow analog circuits to operate with supply voltages as low as 0.5 V. Biasing considerations are given, and robust bias circuits are discussed. For frequency-tunable circuits, a low-voltage MOS varactor tuning technique is presented. The techniques discussed are applied to two different OTA topologies, as well as to an automatically tuned, fifth-order active RC filter. This material is largely based on the work of the authors as described in [1]-[5].

We present our recent results of the 10-bit data driver LSI for 42-inch diagonal TFT-LCD TV with full HD format. To develop data driver LSIs for a true 10-bit TFT-LCD TV with full HD (19201080) format, small chip area, low power consumption, and output uniformity between channels are key problems that must be solved. By applying a two-stage DAC which combines 8-bit resistor-string DAC and 2-bit binary weighted capacitor DAC, the area increase is limited to only 30% compared to the area of 8-bit resistor-string DAC. The output deviation between channels is successfully limited within 5 mV and the driver LSI with 414 outputs consumes the maximum total current of 16 mA when driving 42-inch HDTV panel. We confirmed that the picture with 10-bit shades of gray is much more natural than that with 8-bit shades of gray.

Because of the data correlation in the motion estimation (ME) algorithm of H.264/AVC reference software, it is difficult to implement an efficient ME hardware architecture. In order to make parallel processing feasible, four modified hardware friendly ME workflows are proposed in this paper. Based on these workflows, a scalable full search ME architecture is presented, which has following characteristics: (1) The sum of absolute differences (SAD) results of 44 sub-blocks is accumulated and reused to calculate SADs of bigger sub-blocks. (2) The number of PE groups is configurable. For a search range of MN pixels, where M is width and N is height, up to M PE groups can be configured to work in parallel with a peak processing speed of N16 clock cycles to fulfill a full search variable block size ME (VBSME). (3) Only conventional single port SRAM is required, which makes this architecture suitable for standard-cell-based implementation. A design with 8 PE groups has been realized with TSMC 0.18 µm CMOS technology. The core area is 2.13 mm1.60 mm and clock frequency is 228 MHz in typical condition (1.8 V, 25).

This paper presents method that offers the fast and accurate analysis of large-scale periodic array antennas by conjugate-gradient fast Fourier transform (CG-FFT) combined with an equivalent sub-array preconditioner. Method of moments (MoM) is used to discretize the electric field integral equation (EFIE) and form the impedance matrix equation. By properly dividing a large array into equivalent sub-blocks level by level, the impedance matrix becomes a structure of Three-level Block Toeplitz Matrices. The Three-level Block Toeplitz Matrices are further transformed to Circulant Matrix, whose multiplication with a vector can be rapidly implemented by one-dimension (1-D) fast Fourier transform (FFT). Thus, the conjugate-gradient fast Fourier transform (CG-FFT) is successfully applied to the analysis of a large-scale periodic dipole array by speeding up the matrix-vector multiplication in the iterative solver. Furthermore, an equivalent sub-array preconditioner is proposed to combine with the CG-FFT analysis to reduce iterative steps and the whole CPU-time of the iteration. Some numerical results are given to illustrate the high efficiency and accuracy of the present method.

A novel approach for segmentation of grayscale images, which are color scene originally, is proposed. Many algorithms have been elaborated for a grayscale image segmentation. All those approaches have been discussed in a luminance space, because it has been considered that grayscale images do not have any color information. However, a luminance value has color information as a set of corresponding colors. In this paper, an inverse mapping of luminance values is carried out to CIELAB color space, and the image segmentation for grayscale images is performed based on a distance in the color space. The proposed scheme is applied to a region growing segmentation and the performance is verified.

When the frame size is downscaled for video transcoding, the new motion vector (MV) must be computed. This paper presents an algorithm to utilize the activity measurement by DC value and the number of non-zero quantized DCT coefficients in the residual macroblock to compose the motion vector. It can reduce the complexity for motion estimation and improve the performance of the spatial domain video transcoder.

Driving methods for TFT-OLEDs are explained with their features and classified from the viewpoints of grayscale methods and uniformizing methods. This classification leads us to a novel proposal using time ratio grayscale and current uniformization. This driving method maintains current uniformity and simultaneously overcomes charging shortage of the pixel circuit for low grayscale levels and current variation due to the shift of operating points. Tolerance toward degraded characteristics, linearity of grayscale and luminance uniformity against degraded characteristics are confirmed using circuit simulation.

Volume Graphics Clusters (VG Clusters) have proven to be efficient in a wide range of visualization applications and have also shown promise in some other applications where the image composition device could be fully utilized. The main differentiating feature from other graphics clusters is a specialized image composition device, commercially available as the MPC Image Compositor, which enables the building of do-it-yourself VG Clusters. Although this device is highly scalable, the unidirectional composition flow limits the data subdivision to the quantity of physically available rendering nodes. In addition, the limited buffer memory limits the maximum capable image composition size, therefore limiting its use in large-scale data visualization and high-resolution visualization. To overcome these limitations, we propose and evaluate an image composition mechanism in which additional hardware is used for assisting the image composition process. Because of the synergistic use of two distinct image composition hardware devices we named it "Hybrid Image Composition". Some encouraging results were obtained showing the effectiveness of this solution in improving the VG Cluster 's potential. A low-cost parallel port based hardware barrier is also presented as an efficient method for further enhancing this kind of small-scale VG Cluster. Moreover, this solution has proven to be especially useful in clusters built using low-speed networks, such as Fast Ethernet, which are still in common use.

The presence of the complex scaling behavior in network traffic makes accurate traffic prediction a challenging task. Some conventional prediction tools such as the recursive least square method are not appropriate for network traffic prediction. In this paper we propose a timescale decomposition approach to real time traffic prediction. The raw traffic data is first decomposed into multiple timescales using the à trous Haar wavelet transform. The wavelet coefficients and the scaling coefficients at each scale are predicted independently using the ARIMA model. The predicted wavelet coefficients and scaling coefficient are then combined to give the predicted traffic value. This timescale decomposition approach can better capture the correlation structure of the traffic caused by different network mechanisms, which may not be obvious when examining the raw data directly. The proposed prediction algorithm is applied to real network traffic. It is shown that the proposed algorithm outperforms traffic prediction algorithms in the literature and gives more accurate results.

In this paper, we shall construct mathematical theory based on the concept of set-valued mappings, suitable for available operation of extraordinarily complicated large-scale network systems by introducing some connected-block structures. A fine estimation technique for availability of system behaviors of such network systems are obtained finally in the form of fixed point theorem for a special system of fuzzy-set-valued mappings.

Traffic sign recognition usually consists of two stages: detection and classification. In this paper, we describe the classification stage using the ring-partitioned method. The proposed method uses a specified grayscale image in the pre-processing step and ring-partitioned matching in the matching step. The method does not need carefully prepared many samples of traffic sign images for the training process, alternatively only the standard traffic signs are used as the reference images. The experimental results show the effectiveness of the method in the matching of occluded, rotated, and illumination problems of the traffic sign images with the fast computation time.

In this paper, the electric field radiated by a lightning discharge is derived in the time-frequency domain. By modeling a tortuous and branched lighting discharge, we computed the discrete wavelet transform of the radiated electric field, providing time localization of the fine structure of the field, which is though to be related to the discharge path geometry. By solving the radiated field in the wavelet domain, we aim at simulating the effects of the channel geometry on the victim system.

This paper presents new encoding methods for the binary genetic algorithm (BGA) and new converting methods for the real-coded genetic algorithm (RCGA). These methods are developed for the specific case in which some parameters have to be searched in wide ranges since their actual values are not known. The oversampling effect which occurs at large values in the wide range search are reduced by adjustment of resolutions in mantissa and exponent of real numbers mapped by BGA. Owing to an intrinsic similarity in chromosomal operations, the proposed encoding methods are also applied to RCGA with remapping (converting as named above) from real numbers generated in RCGA. A simple probabilistic analysis and benchmark with two ill-scaled test functions are carried out. System identification of a simple electrical circuit is also undertaken to testify effectiveness of the proposed methods to real world problems. All the optimization results show that the proposed encoding/converting methods are more suitable for problems with ill-scaled parameters or wide parameter ranges for searching.

Embedded systems are used in broad fields. They are one of the indispensable and fundamental technologies in a highly informative society in recent years. As embedded systems are large-scale and complicated, it is prosperous to design and develop a system LSI (Large Scale Integration). The structure of the system LSI has been increasing complexity every year. The degree of improvement of its design productivity has not caught up with the degree of its complexity by conventional methods or techniques. Hence, an idea for the design of a system LSI which has the flow of describing specifications of a system in UML (Unified Modeling Language) and then designing the system in a system level language has already proposed. It is important to establish how to convert from UML to a system level language in specification description or design with the idea. This paper proposes, extracts and verifies transformation rules from UML to SpecC which is one of system level languages. SpecC code has been generated actually from elements in diagrams in UML based on the rules. As an example to verify the rules, "headlights control system of a car" is adopted. SpecC code has been generated actually from elements in diagrams in UML based on the rules. It has been confirmed that the example is executed correctly in simulations. By using the transformation rules proposed in this paper, specification and implementation of a system can be connected seamlessly. Hence, it can improve the design productivity of a system LSI and the productivity of embedded systems.