We have developed a novel self-alignment process using the surface tension of the liquid resin for assembly of electronic and optoelectronic devices. Due to their characteristics of low surface tension, however, the parametric design guidelines are necessary for resin self-alignment capability. In this paper, a shape prediction mathematical model and a numerical method are developed. The developed system is capable of achieving the liquid joint geometry and the parametric design for self-alignment capability. The influences of geometric parameters such as liquid volume, component weight, pad radius, liquid surface tension on the shape of liquid joint are investigated. Furthermore, the parametric design guidelines considered the process-related practical matters of misalignment level, distribution of the supplied liquid volumes and coplanarity deviation includes difference of the height between the pads are provided.

We propose linearization techniques for MMIC amplifiers. The key points of these techniques are increased linearity of a newly-developed low-distortion MESFET (LD-FET) and maximized IP3 by combining the LD-FET with a high-gain depletion-mode MESFET (D-FET) with no increase in power consumption. The LD-FET is characterized by its unique channel dopant-profile prepared by a buried p-type ion-implantation and double n-type ion-implantations with high- and low-acceleration energies. This FET achieves flatter behavior in terms of mutual conductance (gm) compared with conventional MESFETs irrespective of changes in the gate bias voltage (Vgs). A self-alignment/selective ion-implantation process enables the LD-FET and D-FET to be fabricated simultaneously. This process encourages IP3 maximization of the multi-stage amplifier by appropriately combining the advantages of the two differently characterized MESFETs. We fabricated and tested a highly linearized two-stage MMIC amplifier utilizing the proposed techniques, and found that its third-order intermodulation ratio (IMR) performance was 8.7 dB better than that of conventional MMIC amplifiers at an input signal level of -20 dBm with no increase in current dissipation. The configuration constructed by using the proposed techniques equivalently reduces the current dissipation of the second stage to 1/2.72 times that of the conventional configuration, which requires a 2.72 times larger D-FET at the second stage to obtain an 8.7-dB IMR improvement. Furthermore, we were able to improve the IMR by 3.5 dB by optimizing the gate bias conditions for the LD-FET. These results confirm the validity of the proposed techniques.

We have developed a novel self-alignment process using the surface tension of the liquid resin for assembly of electronic or optoelectronic devices. Though the liquid resins have a characteristics as low as one tenth of the surface tension of solder in general, restoring forces for self-alignment capability can be produced by making it constrained on the 3-dimensional pads on chip and substrate. In this paper, its principle and characteristics are described and the relationship between process parameters and joint geometry were examined. And the possibility of self-alignment process was verified by analytic numerical method and scaled-up experiment. A self-alignment accuracy was examined experimentally and show that it became less than 0.4 µm. It can provide a useful information on various parameters involved in joint geometry and optimal design guideline to generate the proper profiles.

A 33-cm-Diagonal High-Resolution(1280 1024RGB, which stands for red, green, and blue) TFT-LCD with low, uniform parasitic capacitance between gate electrodes and source/drain electrodes has been developed using Fully Self-Aligned a-Si TFTs. The fabricated TFT-LCD shows no visible seams between block shot exposure regions, even in the display of gray images. In this paper, we describe(1) our full self-alignment technology for the TFTs, including the fabrication process and the technology for reducing OFF current in the TFTs under illumination, (2) SPICE simulation for estimating pixel voltage shift in the fabricated TFT-LCD, and (3) performance results for the fabricated TFT-LCD.

Recent high-speed bipolar technologies based on SICOS (Sidewall Base Contact Structure) transistors are reviewed. Bipolar device structures that include polysilicon are key technologies for improving circuit characteristics. As the characteristics of the upward operated SICOS transistors are close to those of downward transistors, they can easily be applied in memory cells which have near-perfect soft-error-immunity. Newly developed process technologies for making shallow base and emitter junctions to improve circuit performance are also reviewed. Finally, complementary bipolar technology for low-power and high-speed circuits using pnp transistors, and a quasi-drift base transistor structure suitable for below 0.1 µm emitters are discussed.

High speed GaAs ICs (Integrated Circutis) using FETs (Field Effect Transistors) are reported. As the fabricating techniques, ion implantation processes for both 0.5 µm and 0.2 µm gate FETs using W/Al refractory metal and 0.2 µm recessed gate process with MBE grown epitaxial wafers are shown. These fabrication processes are selected depending on the circuit speed and the integration level. The outline of the circuit design and the examples of ICs, which are developed for 10 Gb/s optical communication systems, are also shown with the obtained characteristics.

Selective epitaxial growth technology has been extended to the base formation of a transistor on the basis of the SATURN (Self-Alignment Technology Utilizing Reserved Nitride) process, a high-speed bipolar LSI processing technology. The formation of a self-aligned base contact, coupled with SIC (Selective Ion-implanted Collector) fabricated by lowenergy ion implantation, has not only narrowed the transistor active regions but has drastically reduced the base width. A final base width of 800 and a maximum cut-off frequency of 31 GHz were achieved.