An arc model has been applied in this paper to study the fundamental interruption environment of a 550 kV SF6 single-break tank circuit breaker. The full differential model takes into account of all important physical mechanisms and is implemented into a commercial Computational Fluid Dynamics (CFD) package, PHOENICS. The model takes a magneto-hydro-dynamics (MHD) approach and the governing equations are solved using the Finite Volume Method (FVM). Through the simulation, the flow velocity vector and mach number for capacitive current switching and short-circuit current breaking are analyzed, and flow dynamic characteristics are obtained. The simulation can provide helpful reference for the design of 550 kV SF6 single-break tank circuit breaker.

Accurate current analysis is required in circuit designs to analyze electromigration failure rate, power consumption, voltage drop, and so on. A charge-based current model for CMOS gates is presented in this paper. The current waveform of a CMOS gate during a transition consists of three components: one occurs when the input changes and the others exist only when the output changes. These three components are characterized by triangular pulses with four parameters which can be easily obtained after timing simulation. This model has been embedded into our switch-level timing simulator to generate the current waveform. The simulated current waveform helps solve the VLSI reliability problems due to electromigration and excess voltage drops in the power buses. When comparing the results obtained by using SPICE with those by our model, we find agreement, especially on the time points at which current pulses occur.

An NMOS 4-phase dynamic logic scheme is described, which is intended to achieve low-power consumption in the deep submicron design. In this scheme, the short-circuit current is eliminated, and moreover, the voltage swing of transition signals is reduced, resulting in enhancing power reduction effectively. First, distinctive features of this 4-phase dynamic logic are specified, as compared with the static CMOS logic and dynamic domino CMOS logic. Then, power simulations are attempted for the 4-phase dynamic logic, static CMOS logic, dynamic CMOS logic, and pass-transistor logic, by using a number of logic modules, which demonstrate that the NMOS 4-phase dynamic logic is the most power-efficient. Moreover, through the gate delay simulation, the capability of how many transistors can be packed in a logic block is also discussed.

As MOSFET sizes and wire widths become very small in recent years, influence of resistive component of interconnects on the estimation of propagation delay and power dissipation can no longer be neglected. In this paper we present formulas of output waveform at driving point and short-circuit power dissipation for static CMOS logic gates driving a CRC π load. By representing the short-circuit current and the current flowing in the resistance of a CRC π load by piece-wise linear functions, a closed-form formula is derived. On the gate delay the error of our formula is less than 8% from SPICE in our experiments. These formulas will contribute to faster estimation of circuit speed and power dissipation of VLSI chips on timing level simulators.