This paper deals with a high-speed digital circuit for discrete cosine transform (DCT). We propose a new algorithm that reduces the number of calculations for partial sum-of-products in the DCT and synthesize the small gate depth circuit of DCT by using carry-propagation-free adders based on redundant binary {1,0,1} representation. The gate depth is only half to one third that of the conventional algorithms with the same number of gates.

This paper describes the imaging method for a human forearm in the microwave transmission CT at 3GHz. To improve the spatial resolution, the correction method of the diffraction effects is adopted and the high directivity antennas are used. A cross-sectional image of the human forearm is obtained in vivo.

A low power bus architecture with Local and Global Charge-Recycling Bus (Local-CRB and Global-CRB) techniques, featuring virtual stacking of the individual bus-capacitance and the dummy capacitor into a series configuration between supply voltage and ground, has been proposed. These Local and Global CRB schemes make it possible to reduce not only each bus-swing but also a total equivalent bus-capacitance of the ultra multi-bit buses running in parallel. The voltage swing of each bus is given by the recycled charge-supplying from the upper adjacent bus capacitance or the dummy capacitor, instead of the power line. The dramatical power reduction was verified by the simulated and measured data. According to these data, if employing the combination of those CRB schemes in a practical chip, the ultra-high data rate of 25 Gb/s can be achieved while maintaining the power dissipation to be less than 300 mW at Vcc3.6 V for the bus width of 512 bit with the bus-capacitance of 14 pF per bit operating at 50 MHz.

This paper presents a low-power 8-valued cellular array VLSI for high-speed image processing based on logical neighborhood operations with 33 windows. This array is useful for performing low-level image processing such as noise removal and edge detection, in intelligent integrated systems where immediate response to input change as well as high throughput is needed. In order to achieve high-speed image processing, template matching for neighborhood operations can be performed in parallel on each row. Each row of the image is operated in a pipelining manner. The direct 8-valued encoding of the matched results for three different 33 masks makes it possible to reduce the number of operations by one-third. In the hardware implementation, the matching cell for logical neighborhood operations can be implemented compactly using MOS transistors with different threshold voltage, which are programmed by multiple ion implants. Moreover, a new literal circuit for detecting multiple-valued signals using a dynamic design style eliminates hazards due to timing skews in the difference of various input voltage levels, so that the dynamic power dissipation of the proposed circuit is greatly reduced. Finally, it is demonstrated that the processing time of the proposed cellular array is reduced to about 40 percent in comparison with that of a corresponding binary circuit when power dissipation/area = 0.3 W/100 mm2.

The main problem in statistical pattern recognition is to design a classifier. Many researchers point out that a finite number of training samples causes the practical difficulties and constraints in designing a classifier. However, very little is known about the performance of a classifier in small training sample size situations. In this paper, we compare the classification performance of the well-known classifiers (k-NN, Parzen, Fisher's linear, Quadratic, Modified quadratic, Euclidean distance classifiers) when the number of training samples is small.

Computing devices have reached data frequencies of 100 MHz, and have created a need for small-amplitude impedance-matched buses. We simulated signal transmission characteristics of two basic driver circuits, push-pull and open-drain,for a synchronous DRAM I/O bus. The push-pull driver caused less signal distortion with parasitic inductance and capacitance of packages, and thus has higher frequency limits than the open-drain GTL type. We describe a bus system using push-pull drivers which operates at over 125 MHz. The bus line is 70 cm with 8 I/O loads distributed along the line, each having 25 nH7pF parasitic inductance and capacitance.

This paper analyses the amplification characteristics of a two-loop controlled switching power amplifier for a digital portable telephone and presents the amplifier which has a flat gain and small phase delay from dc to 100kHz. This amplifier is a modification of a switching regulator and it uses two-loop control to achieve a wideband amplification characteristic. Optimum amplification characteristics, however, can't be designed by using the conventional method for designing a switching regulator because a flat gain and small phase delay in an amplification characteristic has not been considered for most switching regulators. This paper analyses in detail the small-signal transfer functions of the switching power amplifier and shows the behaviour of zero and poles. It also shows the boundary condition of large-signal operation. A new design procedure of a switching power amplifier is presented, and the analytical results are verified by experiments.

Behavior of solutions related to an accuracy exp(-1/ε) is studied. Computer results are given, and examined from the view-point of non-standard analysis. The experimental results raise some important questions on the computer study of slow-fast systems.

This paper addresses onboard processing architecture employing direct regeneration. The advantage of direct regeneration is its hardware simplicity, even though the bit error rate performance is slightly inferior to that of demodulation-remodulation scheme with coherent detection. The channel filtering schemes as well as achievable capacities are examined by computer simulation. It is found that the system with direct regeneration has advantage in channel capacity and transmit earth station e.i.r.p. for small earth stations. A possible configuration of direct regeneration onboard in future satellite systems is proposed.

A theoretical method is required for prediction of mean field strength in land mobile radio systems, instead of the conventional empirical methods. Feasibility study of theoretical prediction using the ray-tracing method, was made in a 1.2GHz band for a model of a small-cell system. Theoretical values showed better agreement with the measured, when diffraction around the side edges of a building is taken into account. Comparison between mean field strengths in summer and winter suggested the seasonal variations in attenuation due to trees.

A precise method for determining AlGaAs/GaAs HBT large-signal circuit parameters is presented. In this method, the parameters are extracted from noise parameters and small-signal S-parameters measured under various bias conditions. The measured noise parameters are fitted to the calculated noise parameters derived from an approximation of Hawkins' equations applied to the macroscopic equivalent circuit. The small-signal S-parameters help to determine the large-signal circuit parameters. The derived large-signal parameters were used to design an HBT oscillator. The simulated results using these parameters were in good agreement with the fabricated device performance.

GaAs MESFETs with a p-buffer layer (or a buried p-layer) are important devices for high-speed GaAs ICs. To study what conditions are required as a good substrate for ICs, we have investigated, by two-dimensional simulation, small-signal parameters and drain-current transients of GaAs MESFETs with a p-buffer layer on the semi-insulating substrate. It is shown that the introduction of a p-buffer layer is effective to improve the transconductance and the cuttoff frequeycy. These parameters are not degrade even if the p-layer doping is increased and a neurtral p-region exists. It is also shown that drain-current drifts and hysteresis in I-V curves can occur in a case with a p-buffer layer, too. It is concluded that the introduction of a relatively highly-doped p-layer on a substrate with low acceptor and electron trap (EL2) densities is effective to realize the stable and high performance of GaAs MESFETs.

This paper describes the structure and properties of superconductive small antennas with thin-film matching circuits. These circuits make it possible to realize small antennas, 38 mm20 mm16 mm in size. This is one quarter the length of our previously reported ceramic antennas. The actual gain of this antennas was -4.5 dBi at 470 MHz. This value is 5.5 dB higher than that of Cu antennas with exactly the same structure.