A Mach-Zehnder optical modulator with the tunable multimode interference coupler was fabricated using Ti-diffused LiNbO3. The modulation extinction ratio could be voltage controlled to maximize up to 50 dB by tuning the coupler. Optical single-sideband modulation was also achieved with a sideband suppression ratio of more than 30 dB.

Photocatalytic TiO2 films were prepared by reactive gas flow sputtering (GFS), which enables sputter-deposition at a high pressure of about 100 Pa. A pure Ti tube was used as the target, and the O2 gas was supplied in front of the substrate, resulting in a very stable discharge and a high deposition rate of 80 nm/min. The crystal structure and morphology of TiO2 films were found to strongly depend on the flow rate of O2 gas during sputtering. Polycrystalline films composed of rutile and anatase crystallites were deposited at a low O2 flow rate of less than 2 sccm when Ar flow rate was set at 300 sccm, and amorphous films were deposited at higher O2 flow rates. Polycrystalline films composed of very small crystallites showed high levels of photocatalytic activity, while amorphous films showed no activity.

Bidirectional reflection distribution functions (BRDFs) of commercially pure titanium sheets with three different kinds of surface morphology were measured. Those experimental BRDFs were analyzed by using Phong's reflection model. Topographic measurements of the specimens' surfaces were performed with using a stylus-method. An explicit microfacet model based on topographic data was proposed. With using the explicit microfacet model and geometrical optics the calculated BRDFs were obtained and then compared with the experimental BRDFs. Both of them were in a good agreement. Through this comparison physical meanings of Phong's reflection model were discussed. We concluded that with using the explicit microfacet model it will be possible to calculate the BRDF of the materials' surface in arbitrary illumination conditions and that this modeling will be useful to develop new aesthetic surface appearance in material industries, computer graphics, architectural design and surface science.

Epitaxial SrTiO3(STO) film on epitaxial (Ti,Al)N/Si(100) was successfully obtained using a Ti-buffer layer. The SrTiO3 film was (100) oriented and grew in parallel epitaxial relationship (cube-on-cube), i.e., (100)SrTiO3//(100)(Ti,Al)N//(100)Si, <110> SrTiO3//<110> (Ti,Al)N//<110> Si. The Ti-buffer layer was grown on (Ti,Al)N by magnetron sputtering, and the thickness of the buffer layer was 2-10 nm. After the STO film was sputtered, the Ti-buffer layer was changed to polycrystalline anatase-TiO2.

A two-dimensional self-aligned silicide (SALICIDE) model has been developed using the general-purpose process simulator OPUS. A new two-dimensional growth model is proposed. Utilizing a newly-difined effective silicide thickness, the model accounts both silicon-diffusion and metal-diffusion limited silicide growth. Silicide lateral-growth along a sidewall spacer is successfully simulated for Si-diffusion limited silicide growth. Complete MOSFET process simulation with a SALICIDE process is demonstrated for the first time.

A novel CMOS structure has been developed using Ti-salicide PSD transistor formed by a new self-aligned method. Both N-channel and P-channel PSD transistors exhibit excellent short-channel behaviors down to the sub-half-micrometer region with shallow S/D junctions formed by dopant diffusion from polysilicons. New salicide process has been developed for the PSD structure and can effectively reduce the sheet resistances of the S/D polysilicon and the polysilicon gate to as low as 45Ω/. As a result, the low resistive local interconnects can be successfully implemented by the Ti-salicide S/D polysilicon merged with contacts by self-alignment. More-over it is found that shallow Ti-salicide S/D junctions with the PSD structure can achieve approximately 12 orders of magnitude lower area leakage current than that of the conventional implanted S/D junctions by eliminating implanted damage and preventing penetration of silicide into junctions with the elevated structure of S/D polysilicon layer. Furthermore CMOS ring oscillators having PSD transistors with an effective channel length of 0.4 µm were fabricated using the salicided S/D polysilicon as a local interconnect between the N+ and the P+ regions, and successfully operated with a propagation delay time of 50 ps/stage at a supply voltage of 5 V.

Phosphorus-doped amorphous or polycrystalline silicon can yield a conformal, low resistance, thermallystable plug for the high-aspect-ratio, sub-half-micron contactholes found in current development prototypes of future 64 and 256 Mega-bit DRAMs. When directly contacted to a silicide layer, however, such as WSix found in polycide gate or bit line metallization/contact structures, the outdiffusion of phosphorus from the doped-silicon layer into the silicide can occur, resulting in an increase in resistance. The characteristics of both the doped-silicon and WSix layers influence the outdiffusion. The grain size of the doped silicon appears to control diffusion at the WSix/doped-silicon interface while the transition of WSix from an as-deposited amorphous to a post-annealed polycrystalline state appears to help cause uniform phosphorus diffusion throughout the silicide film. The results of phosphorus pre-doping of the silicide to reduce the effects of outdiffusion are dependent upon the relative material volumes and interfacial areas of the layers. Due to the effectiveness of the TiN barrier layer/Ti contact layer structure used in Al-based contacts, Ti and TiN were evaluated on their ability to prevent phosphorus outdiffusion. Ti reacts easily with doped silicon and to some extent with WSix, thereby allowing phosphorus to outdiffuse through the TiSix into the overlying WSix. TiN, however, is very effective in preventing phosphorus outdiffusion and preserving polycide interface smoothness. A WSix/TiN/Ti metallization layer on an in situ-doped (ISD) silicon layer with ISD silicon-plugged contactholes yields contact resistances comparable to P+-implanted or non-implanted WSix layers on similar ISD layers/plugs for contact sizes greater than approximately 0.5 µm but for contacts of 0.4 µm or below the trend in contact resistance is lowest for the polycide with TiN barrier/Ti contact interlayers. A 20 nm-thick TiN film retains its barrier characteristics even after a 4-hour 850 anneal and is applicable to the silicide-on-doped-silicon structures of future DRAM and other ULSI devices.