IEICE TRANSACTIONS on Electronics
Dynamic Floating Body Control SOI CMOS for Power Managed Multimedia ULSIs
Summary :
A novel body potential-controlling technique for floating SOI CMOS circuits is proposed and verified in this study. High-speed operation is realized with a small chip size by using body-floating SOI transistors. The use of this technique allows the threshold voltage of the body-floating transistors to be varied transitionally. Therefore, the standby current of SOI CMOS logic is reduced to less than 1/50th of that required by the non-controlled operation of the body potential, and the logic operates at a high speed during the active period. There is no speed penalty for the recovery operation from the standby mode. This technique supports sub-1 V operation, which will be required by future battery-operated devices with wide-range covering.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E84-C No.2 pp.253-259
- Publication Date
- 2001/02/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Integrated Electronics
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Fukashi MORISHITA, Kazutami ARIMOTO, Kazuyasu FUJISHIMA, Hideyuki OZAKI, Tsutomu YOSHIHARA, "Dynamic Floating Body Control SOI CMOS for Power Managed Multimedia ULSIs" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 2, pp. 253-259, February 2001, doi: .
Abstract: A novel body potential-controlling technique for floating SOI CMOS circuits is proposed and verified in this study. High-speed operation is realized with a small chip size by using body-floating SOI transistors. The use of this technique allows the threshold voltage of the body-floating transistors to be varied transitionally. Therefore, the standby current of SOI CMOS logic is reduced to less than 1/50th of that required by the non-controlled operation of the body potential, and the logic operates at a high speed during the active period. There is no speed penalty for the recovery operation from the standby mode. This technique supports sub-1 V operation, which will be required by future battery-operated devices with wide-range covering.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_2_253/_p
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@ARTICLE{e84-c_2_253,
author={Fukashi MORISHITA, Kazutami ARIMOTO, Kazuyasu FUJISHIMA, Hideyuki OZAKI, Tsutomu YOSHIHARA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Dynamic Floating Body Control SOI CMOS for Power Managed Multimedia ULSIs},
year={2001},
volume={E84-C},
number={2},
pages={253-259},
abstract={A novel body potential-controlling technique for floating SOI CMOS circuits is proposed and verified in this study. High-speed operation is realized with a small chip size by using body-floating SOI transistors. The use of this technique allows the threshold voltage of the body-floating transistors to be varied transitionally. Therefore, the standby current of SOI CMOS logic is reduced to less than 1/50th of that required by the non-controlled operation of the body potential, and the logic operates at a high speed during the active period. There is no speed penalty for the recovery operation from the standby mode. This technique supports sub-1 V operation, which will be required by future battery-operated devices with wide-range covering.},
keywords={},
doi={},
ISSN={},
month={February},}
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TY - JOUR
TI - Dynamic Floating Body Control SOI CMOS for Power Managed Multimedia ULSIs
T2 - IEICE TRANSACTIONS on Electronics
SP - 253
EP - 259
AU - Fukashi MORISHITA
AU - Kazutami ARIMOTO
AU - Kazuyasu FUJISHIMA
AU - Hideyuki OZAKI
AU - Tsutomu YOSHIHARA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2001
AB - A novel body potential-controlling technique for floating SOI CMOS circuits is proposed and verified in this study. High-speed operation is realized with a small chip size by using body-floating SOI transistors. The use of this technique allows the threshold voltage of the body-floating transistors to be varied transitionally. Therefore, the standby current of SOI CMOS logic is reduced to less than 1/50th of that required by the non-controlled operation of the body potential, and the logic operates at a high speed during the active period. There is no speed penalty for the recovery operation from the standby mode. This technique supports sub-1 V operation, which will be required by future battery-operated devices with wide-range covering.
ER -
English
