This paper describes an adaptive fingerprint-sensing scheme for a user authentication system with a fingerprint sensor LSI to obtain high-quality fingerprint images suitable for identification. The scheme is based on novel evaluation indexes of fingerprint-image quality and adjustable analog-to-digital (A/D) conversion. The scheme adjusts dynamically an A/D conversion range of the fingerprint sensor LSI while evaluating the image quality during real-time fingerprint-sensing operation. The evaluation indexes pertain to the contrast and the ridgelines of a fingerprint image. The A/D conversion range is adjusted by changing quantization resolution and offset. We developed a fingerprint sensor LSI and a user authentication system to evaluate the adaptive fingerprint-sensing scheme. The scheme obtained a fingerprint image suitable for identification and the system achieved an accurate identification rate with 0.36% of the false rejection rate (FRR) at 0.075% of the false acceptance rate (FAR). This confirms that the scheme is very effective in achieving accurate identification.

The effectiveness of model adaptation in dialogue speech synthesis is explored. The proposed adaptation method is based on a conversion from a base model learned with a large dataset into a target, dialogue-style speech model. The proposed method is shown to improve the intelligibility of synthesized dialogue speech, while maintaining the speaking style of dialogue.

This paper presents a simple 3-D array configuration for high-resolution 2-D Direction-Of-Arrival (DOA) estimation. Planar array structures like Uniform Rectangular Array (URA) or Uniform Circular Array (UCA) often well estimate azimuth angle but cannot well estimate elevation angle because of short antenna aperture in elevation direction. One may put more number of array elements to improve elevation angle estimation accuracy, however it will require very large hardware and software cost. This paper presents a simple 3-D array structure for high-resolution 2-D DOA estimation only by modifying the height of some array elements in a planar array. Based on the analysis of Cramer-Rao Lower Bound (CRLB) formulation and its dependency on the height of array elements, we develop a simple 3-D array structure which improves elevation angle estimation accuracy while preserving azimuth angle estimation accuracy.

In a downlink multi-user multiple-input multiple-output (MU-MIMO) system, the vector perturbation (VP) method, which is one of the non-linear precoding methods, is a promising technique with which to maximize the channel capacity. In the VP method, the receiver requires the modulo operation to remove the perturbation signal added at the transmitter. However, owing to noise, the modulo operation may not run correctly which makes the soft demapper produce unreliable log-likelihood ratios (LLRs), resulting in a degradation of system throughput. To enhance the throughput performance, we propose a method that expands the basic perturbation interval and adaptively controls the expansion rate according to the modulation and coding scheme (MCS). The optimum expansion rate is derived by link-level simulation and the system throughput is measured by system-level simulation. The system-level simulation results show that the proposed VP method can obtain higher throughput than the conventional VP method.

An inverter is a circuit which outputs ¬ x1, ¬ x2, ..., ¬ xn for any Boolean inputs x1, x2, ..., xn. We consider constructing an inverter with AND gates and OR gates and a few NOT gates. Beals, Nishino and Tanaka have given a construction of an inverter which has size O(nlog n) and depth O(log n) and uses ⌈ log (n+1) ⌉ NOT gates. In this paper we give a construction of an inverter which has size O(n) and depth log 1+o(1)n and uses log 1+o(1)n NOT gates. This is the first negation-limited inverter of linear size using only o(n) NOT gates. We also discuss implications of our construction for negation-limited circuit complexity.

A new threshold circuit technique is proposed for a vibration sensing circuit that operates at a nanowatt power level. The sensing circuits that use sample-and-hold require a clock signal, and they consume power to generate a signal. In the use of a Schmitt trigger circuit that does not use a clock signal, a sink current flows when thresholding the analog signal output. The requirements for millimeter-sized wireless sensor nodes are an average power on the order of a nanowatt and a signal transition time of less than 1 ms. To meet these requirements, our circuit limits the sink current with a nanoampere-level current source. The chattering caused by current limiting is suppressed by feeding back the change in output voltage to the limiting current. The increase in the signal transition time that is caused by current limiting is reduced by accelerating the discharge of the load capacitance. For a test chip fabricated in the 0.35-µm CMOS process, the proposed threshold circuits operate without chattering and the average powers are 0.7-3 nW. The signal transition times are estimated in a circuit simulation to be 65-97 µs. The proposed circuit has 1/150th the power-delay product with no time interval of the sensing operation under the condition that the time interval is 1s. These results indicate that, the proposed threshold circuits are suitable for vibration sensing in millimeter-sized wireless sensor nodes.

Transitional fundamental frequency (F0) characteristics comprise a crucial part of F0 dynamics in singing. This paper examines the F0 characteristics during the note transition period. An analysis of the singing voice of a professional baritone strongly suggests that asymmetries exist in the mechanisms used for controlling rising and falling. Specifically, the F0 contour in rising transitions can be modeled as a step response from a critically-damped second-order linear system with fixed average/maximum speed of change, whereas that in falling transitions can be modeled as a step response from an underdamped second-order linear system with fixed transition time. The validity of the model is examined through auditory experiments using synthesized singing voice.

This paper presents an ultra-low power and temperature-independent voltage detector with a post-fabrication programming method, and presents a theoretical analysis and measurement results. The voltage detector is composed of a programmable voltage detector and a glitch-free voltage detector to realize both programmable and glitch-free operation. The programmable voltage detector enables the programmable detection voltages in the range from 0.52V to 0.85V in steps of less than 49mV. The glitch-free voltage detector enables glitch-free operation when the supply voltage is near 0V. A multiple voltage copier (MVC) in the programmable voltage detector is newly proposed to eliminate the tradeoff between the temperature dependence and power consumption. The design consideration and a theoretical analysis of the MVC are introduced to clarify the relationship between the current in the MVC and the accuracy of the duplication. From the analysis, the tradeoff between the duplication error and the current of MVC is introduced. The proposed voltage detector is fabricated in a 250nm CMOS process. The measurement results show that the power consumption is 248pW and the temperature coefficient is 0.11mV/°C.

By focusing on the recent swing to the centralized approach by the software defined network (SDN), this paper presents a novel network architecture for refactoring the current distributed Internet protocol (IP) by not only utilizing the SDN itself but also implementing its cooperation with the optical transport layer. The first IP refactoring is for flexible network topology reconfiguration: the global routing and explicit routing functions are transferred from the distributed routers to the centralized SDN. The second IP refactoring is for cost-efficient maintenance migration: we introduce a resource portable IP router that can behave as a shared backup router by cooperating with the optical transport path switching. Extensive evaluations show that our architecture makes the current IP network easier to configure and more scalable. We also validate the feasibility of our proposal.

The next generation wireless LAN standard IEEE 802.11ax aims to provide improved throughput performance in dense environments. We have proposed an efficient channel sounding mechanism for DL-MU-MIMO that has been adopted as a new sounding protocol in the 802.11ax standard. In this paper, we evaluate the overhead reduction in the 802.11ax sounding protocol compared with the 802.11ac sounding protocol. Sounding is frequently performed to obtain accurate channel information from the associated stations in order to improve overall system throughput. However, there is a trade-off between accurate channel information and the overhead incurred due to frequent sounding. Therefore, the sounding interval is an important factor that determines system throughput in DL-MU-MIMO transmission. We also evaluate the effect of sounding interval on the system throughput performance using both sounding protocols and provide a comparative analysis of the performance improvement.

It is well known that spatially coupled (SC) codes with erasure-BP decoding have powerful error correcting capability over memoryless erasure channels. However, the decoding performance of SC-codes significantly degrades when they are used over burst erasure channels. In this paper, we propose band splitting permutations (BSP) suitable for (l,r,L) SC-codes. The BSP splits a diagonal band in a base matrix into multiple bands in order to enhance the span of the stopping sets in the base matrix. As theoretical performance guarantees, lower and upper bounds on the maximal burst correctable length of the permuted (l,r,L) SC-codes are presented. Those bounds indicate that the maximal correctable burst ratio of the permuted SC-codes is given by λmax≃1/k where k=r/l. This implies the asymptotic optimality of the permuted SC-codes in terms of burst erasure correction.

This paper describes pixel-parallel image-matching circuit schemes that provide the optimal binarization, the high-speed low-power comparison, and the accurate matching of fingerprint images needed for fingerprint verification. Image binarizing is adjusted adaptively during the fingerprint sensing operation. The obtained image is compared with the template in the pixel array, and the results from all of the pixels are totaled by a variable-delay circuit at high speed and low power. For accurate matching, the image is scanned by shifting it in the pixel array while maintaining whole image. The experimental results demonstrate that the proposed schemes provide optimal binary images of most fingers under any condition and environment, 11-µs 147-µW totaling of results from 20,584 pixels, and wide-range image scanning and accurate matching for fingerprint images. These schemes are effective for fast and low-power fingerprint verification for a single-chip fingerprint sensor and identifier.

The circuit satisfiability problem has been intensively studied since Ryan Williams showed a connection between the problem and lower bounds for circuit complexity. In this letter, we present a #SAT algorithm for synchronous Boolean circuits of n inputs and s gates in time $2^{nleft(1 - rac{1}{2^{O(s/n)}} ight)}$ if s=o(n log n).

This paper presents a method of synthesizing covariance matrix elements of array input signal for high resolution 2-D Direction-Of-Arrival (DOA) estimation via antenna (sensor) switching. Antenna array generally has the same number of array elements and receiver modules which often leads large receiver hardware cost. Two of the authors have already studied a way of antenna switching to reduce receiver cost, but it can be applied only for periodic incident signals like sinusoid. In this paper, we propose two simple methods of DOA estimation from sparse data by synthesizing covariance matrix elements of array input signal via antenna switching, which can also be applied to DOA estimation of antiperiodic incident signals. Performance of the proposed approach is evaluated in detail through some computer simulation.

A new postprocessing method using interpolated n-gram model for Japanese documents is proposed. The method has the advantages over conventional approaches in enabling high-speed, knowledge-free processing. In parameter estimation of an n-gram model for a large size of vocabulary, it is difficult to obtain sufficient training samples. To overcome poverty of samples, two smoothing methods for Japanese character trigram model are evaluated, and the superiority of deleted interpolation method is shown by using perplexity. A document recognition system based on the trigram model is constructed, which finds maximum likelihood solutions through Viterbi algorithm. Experimental results for three kinds of documents show that the performance is high when using deleted interpolation method for smoothing. 90% of OCR errors are corrected for the documents similar to training text data, and 75% of errors are corrected for the documents not so similar to training text data.

In this paper, we will present analysis on the fault erasure BP decoders based on the density evolution. In the fault BP decoder, the messages exchanged in a BP process are stochastically corrupted due to unreliable logic gates and flip-flops; i.e., we assume circuit components with transient faults. We derived a set of the density evolution equations for the fault erasure BP processes. Our density evolution analysis reveals the asymptotic behaviors of the estimation error probability of the fault erasure BP decoders. In contrast to the fault free cases, it is observed that the error probabilities of the fault erasure BP decoder converge to positive values, and that there exists a discontinuity in an error curve corresponding to the fault BP threshold. It is also shown that an message encoding technique provides higher fault BP thresholds than those of the original decoders at the cost of increased circuit size.

A framework for generating facial expressions from emotional states in daily conversation is described. It provides a mapping between emotional states and facial expressions, where the former is represented by vectors with psychologically-defined abstract dimensions, and the latter is coded by the Facial Action Coding System. In order to obtain the mapping, parallel data with rated emotional states and facial expressions were collected for utterances of a female speaker, and a neural network was trained with the data. The effectiveness of proposed method is verified by a subjective evaluation test. As the result, the Mean Opinion Score with respect to the suitability of generated facial expression was 3.86 for the speaker, which was close to that of hand-made facial expressions.

This paper describes logic and analog test schemes that improve the testability of a pixel-parallel fingerprint identification circuit. The pixel contains a processing circuit and a capacitive fingerprint sensor circuit. For the logic test, we propose a test method using a pseudo scan circuit to check the processing circuits of all pixels simultaneously. In the analog test, the sensor circuit employs dummy capacitance to mimic the state of a finger touching the chip. This enables an evaluation of the sensitivity of all sensor circuits on logical LSI tester without touching the chip with a finger. To check the effectiveness of the schemes, we applied them to a pixel array in a fingerprint identification LSI. The pseudo scan circuit achieved a 100% failure-detection rate for the processing circuit. The analog test determines that the sensitivities of the sensor circuit in all pixels are in the proper range. The results of the tests confirmed that the proposed schemes can completely detect defects in the circuits. Thus, the schemes will pave the way to logic and analog tests of chips integrating highly functional devices stacked on a LSI.

This paper presents fingerprint image enhancement and rotation schemes that improve the identification accuracy with the pixel-parallel processing of pixels. In the schemes, the range of the fingerprint sensor is adjusted to the finger state, the captured image is retouched to obtain the suitable image for identification, and the image is rotated to the correct angle on the pixel array. Sensor and pixel circuits that provide these operations were devised and a test chip was fabricated using 0.25-µm CMOS and the sensor process. It was confirmed in 150,000 identification tests that the schemes reduce the false rejection rate to 6.17% from 30.59%, when the false acceptance rate is 0.1%.